de2_ccd_pip.hier_info

altera de2 开发板 vga lcd控制quatus 工程

GPIO_0[23] <= GPIO_0~21
GPIO_0[24] <= GPIO_0~22
GPIO_0[25] <= GPIO_0~23
GPIO_0[26] <= GPIO_0~24
GPIO_0[27] <= <UNC>
GPIO_0[28] <= GPIO_0~25
GPIO_0[29] <= GPIO_0~26
GPIO_0[30] <= GPIO_0~27
GPIO_0[31] <= GPIO_0~28
GPIO_0[32] <= <UNC>
GPIO_0[33] <= GPIO_0~29
GPIO_0[34] <= I2S_LCM_Config:u9.I2S_SDAT
GPIO_0[35] <= GPIO_0~30
GPIO_1[11] <= GPIO_1~32
GPIO_1[14] <= I2C_CCD_Config:u7.I2C_SCLK
GPIO_1[15] <= I2C_CCD_Config:u7.I2C_SDAT
GPIO_1[16] <= <UNC>
GPIO_1[17] <= <UNC>
GPIO_1[18] <= <UNC>
GPIO_1[19] <= <UNC>
GPIO_1[31] <= GPIO_1~33
GPIO_1[34] <= I2C_CCD_Config:u8.I2C_SCLK
GPIO_1[35] <= I2C_CCD_Config:u8.I2C_SDAT


|DE2_CCD_PIP|LCM_PLL:p0
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|DE2_CCD_PIP|LCM_PLL:p0|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~2.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1]~1.DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|DE2_CCD_PIP|LCM_Controller:u0
iRed[0] => LCM_DATA~15.DATAB
iRed[1] => LCM_DATA~14.DATAB
iRed[2] => LCM_DATA~13.DATAB
iRed[3] => LCM_DATA~12.DATAB
iRed[4] => LCM_DATA~11.DATAB
iRed[5] => LCM_DATA~10.DATAB
iRed[6] => LCM_DATA~9.DATAB
iRed[7] => LCM_DATA~8.DATAB
iGreen[0] => LCM_DATA~7.DATAB
iGreen[1] => LCM_DATA~6.DATAB
iGreen[2] => LCM_DATA~5.DATAB
iGreen[3] => LCM_DATA~4.DATAB
iGreen[4] => LCM_DATA~3.DATAB
iGreen[5] => LCM_DATA~2.DATAB
iGreen[6] => LCM_DATA~1.DATAB
iGreen[7] => LCM_DATA~0.DATAB
iBlue[0] => LCM_DATA~7.DATAA
iBlue[1] => LCM_DATA~6.DATAA
iBlue[2] => LCM_DATA~5.DATAA
iBlue[3] => LCM_DATA~4.DATAA
iBlue[4] => LCM_DATA~3.DATAA
iBlue[5] => LCM_DATA~2.DATAA
iBlue[6] => LCM_DATA~1.DATAA
iBlue[7] => LCM_DATA~0.DATAA
LCM_DATA[0] <= LCM_DATA~15.DB_MAX_OUTPUT_PORT_TYPE
LCM_DATA[1] <= LCM_DATA~14.DB_MAX_OUTPUT_PORT_TYPE
LCM_DATA[2] <= LCM_DATA~13.DB_MAX_OUTPUT_PORT_TYPE
LCM_DATA[3] <= LCM_DATA~12.DB_MAX_OUTPUT_PORT_TYPE
LCM_DATA[4] <= LCM_DATA~11.DB_MAX_OUTPUT_PORT_TYPE
LCM_DATA[5] <= LCM_DATA~10.DB_MAX_OUTPUT_PORT_TYPE
LCM_DATA[6] <= LCM_DATA~9.DB_MAX_OUTPUT_PORT_TYPE
LCM_DATA[7] <= LCM_DATA~8.DB_MAX_OUTPUT_PORT_TYPE
LCM_VSYNC <= mVGA_V_SYNC.DB_MAX_OUTPUT_PORT_TYPE
LCM_HSYNC <= mVGA_H_SYNC.DB_MAX_OUTPUT_PORT_TYPE
LCM_DCLK <= iCLK.DB_MAX_OUTPUT_PORT_TYPE
LCM_GRST <= <VCC>
LCM_SHDB <= <VCC>
oDATA_REQ <= mDATA_REQ.DB_MAX_OUTPUT_PORT_TYPE
iCLK => MOD_3[1].CLK
iCLK => MOD_3[0].CLK
iCLK => Pre_MOD_3[1].CLK
iCLK => Pre_MOD_3[0].CLK
iCLK => mDATA_REQ.CLK
iCLK => H_Cont[10].CLK
iCLK => H_Cont[9].CLK
iCLK => H_Cont[8].CLK
iCLK => H_Cont[7].CLK
iCLK => H_Cont[6].CLK
iCLK => H_Cont[5].CLK
iCLK => H_Cont[4].CLK
iCLK => H_Cont[3].CLK
iCLK => H_Cont[2].CLK
iCLK => H_Cont[1].CLK
iCLK => H_Cont[0].CLK
iCLK => mVGA_H_SYNC.CLK
iCLK => V_Cont[10].CLK
iCLK => V_Cont[9].CLK
iCLK => V_Cont[8].CLK
iCLK => V_Cont[7].CLK
iCLK => V_Cont[6].CLK
iCLK => V_Cont[5].CLK
iCLK => V_Cont[4].CLK
iCLK => V_Cont[3].CLK
iCLK => V_Cont[2].CLK
iCLK => V_Cont[1].CLK
iCLK => V_Cont[0].CLK
iCLK => mVGA_V_SYNC.CLK
iCLK => LCM_DCLK.DATAIN
iRST_N => mDATA_REQ.ACLR
iRST_N => Pre_MOD_3[0].ACLR
iRST_N => Pre_MOD_3[1].ACLR
iRST_N => MOD_3[0].ACLR
iRST_N => MOD_3[1].ACLR
iRST_N => mVGA_H_SYNC.ACLR
iRST_N => H_Cont[0].ACLR
iRST_N => H_Cont[1].ACLR
iRST_N => H_Cont[2].ACLR
iRST_N => H_Cont[3].ACLR
iRST_N => H_Cont[4].ACLR
iRST_N => H_Cont[5].ACLR
iRST_N => H_Cont[6].ACLR
iRST_N => H_Cont[7].ACLR
iRST_N => H_Cont[8].ACLR
iRST_N => H_Cont[9].ACLR
iRST_N => H_Cont[10].ACLR
iRST_N => V_Cont[10].ACLR
iRST_N => V_Cont[9].ACLR
iRST_N => V_Cont[8].ACLR
iRST_N => V_Cont[7].ACLR
iRST_N => V_Cont[6].ACLR
iRST_N => V_Cont[5].ACLR
iRST_N => V_Cont[4].ACLR
iRST_N => V_Cont[3].ACLR
iRST_N => V_Cont[2].ACLR
iRST_N => V_Cont[1].ACLR
iRST_N => V_Cont[0].ACLR
iRST_N => mVGA_V_SYNC.ACLR


|DE2_CCD_PIP|VGA_Controller:u1
iRed[0] => oVGA_R~12.DATAB
iRed[1] => oVGA_R~11.DATAB
iRed[2] => oVGA_R~10.DATAB
iRed[3] => oVGA_R~9.DATAB
iRed[4] => oVGA_R~8.DATAB
iRed[5] => oVGA_R~7.DATAB
iRed[6] => oVGA_R~6.DATAB
iRed[7] => oVGA_R~5.DATAB
iRed[8] => oVGA_R~4.DATAB
iRed[9] => oVGA_R~3.DATAB
iGreen[0] => oVGA_G~9.DATAB
iGreen[1] => oVGA_G~8.DATAB
iGreen[2] => oVGA_G~7.DATAB
iGreen[3] => oVGA_G~6.DATAB
iGreen[4] => oVGA_G~5.DATAB
iGreen[5] => oVGA_G~4.DATAB
iGreen[6] => oVGA_G~3.DATAB
iGreen[7] => oVGA_G~2.DATAB
iGreen[8] => oVGA_G~1.DATAB
iGreen[9] => oVGA_G~0.DATAB
iBlue[0] => oVGA_B~9.DATAB
iBlue[1] => oVGA_B~8.DATAB
iBlue[2] => oVGA_B~7.DATAB
iBlue[3] => oVGA_B~6.DATAB
iBlue[4] => oVGA_B~5.DATAB
iBlue[5] => oVGA_B~4.DATAB
iBlue[6] => oVGA_B~3.DATAB
iBlue[7] => oVGA_B~2.DATAB
iBlue[8] => oVGA_B~1.DATAB
iBlue[9] => oVGA_B~0.DATAB
oRequest <= oRequest~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[0] <= oCoord_X[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[1] <= oCoord_X[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[2] <= oCoord_X[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[3] <= oCoord_X[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[4] <= oCoord_X[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[5] <= oCoord_X[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[6] <= oCoord_X[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[7] <= oCoord_X[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[8] <= oCoord_X[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_X[9] <= oCoord_X[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[0] <= oCoord_Y[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[1] <= oCoord_Y[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[2] <= oCoord_Y[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[3] <= oCoord_Y[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[4] <= oCoord_Y[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[5] <= oCoord_Y[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[6] <= oCoord_Y[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[7] <= oCoord_Y[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[8] <= oCoord_Y[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oCoord_Y[9] <= oCoord_Y[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[0] <= oVGA_R~12.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[1] <= oVGA_R~11.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[2] <= oVGA_R~10.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[3] <= oVGA_R~9.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[4] <= oVGA_R~8.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[5] <= oVGA_R~7.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[6] <= oVGA_R~6.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[7] <= oVGA_R~5.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[8] <= oVGA_R~4.DB_MAX_OUTPUT_PORT_TYPE
oVGA_R[9] <= oVGA_R~3.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[0] <= oVGA_G~9.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[1] <= oVGA_G~8.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[2] <= oVGA_G~7.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[3] <= oVGA_G~6.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[4] <= oVGA_G~5.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[5] <= oVGA_G~4.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[6] <= oVGA_G~3.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[7] <= oVGA_G~2.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[8] <= oVGA_G~1.DB_MAX_OUTPUT_PORT_TYPE
oVGA_G[9] <= oVGA_G~0.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[0] <= oVGA_B~9.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[1] <= oVGA_B~8.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[2] <= oVGA_B~7.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[3] <= oVGA_B~6.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[4] <= oVGA_B~5.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[5] <= oVGA_B~4.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[6] <= oVGA_B~3.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[7] <= oVGA_B~2.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[8] <= oVGA_B~1.DB_MAX_OUTPUT_PORT_TYPE
oVGA_B[9] <= oVGA_B~0.DB_MAX_OUTPUT_PORT_TYPE
oVGA_H_SYNC <= oVGA_H_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
oVGA_V_SYNC <= oVGA_V_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
oVGA_SYNC <= <GND>
oVGA_BLANK <= oVGA_BLANK~0.DB_MAX_OUTPUT_PORT_TYPE
oVGA_CLOCK <= iCLK.DB_MAX_OUTPUT_PORT_TYPE
iCLK => oRequest~reg0.CLK
iCLK => oCoord_X[9]~reg0.CLK
iCLK => oCoord_X[8]~reg0.CLK
iCLK => oCoord_X[7]~reg0.CLK
iCLK => oCoord_X[6]~reg0.CLK
iCLK => oCoord_X[5]~reg0.CLK
iCLK => oCoord_X[4]~reg0.CLK
iCLK => oCoord_X[3]~reg0.CLK
iCLK => oCoord_X[2]~reg0.CLK
iCLK => oCoord_X[1]~reg0.CLK
iCLK => oCoord_X[0]~reg0.CLK
iCLK => oCoord_Y[9]~reg0.CLK
iCLK => oCoord_Y[8]~reg0.CLK
iCLK => oCoord_Y[7]~reg0.CLK
iCLK => oCoord_Y[6]~reg0.CLK
iCLK => oCoord_Y[5]~reg0.CLK
iCLK => oCoord_Y[4]~reg0.CLK
iCLK => oCoord_Y[3]~reg0.CLK
iCLK => oCoord_Y[2]~reg0.CLK
iCLK => oCoord_Y[1]~reg0.CLK
iCLK => oCoord_Y[0]~reg0.CLK
iCLK => H_Cont[9].CLK
iCLK => H_Cont[8].CLK
iCLK => H_Cont[7].CLK
iCLK => H_Cont[6].CLK
iCLK => H_Cont[5].CLK
iCLK => H_Cont[4].CLK
iCLK => H_Cont[3].CLK
iCLK => H_Cont[2].CLK
iCLK => H_Cont[1].CLK
iCLK => H_Cont[0].CLK
iCLK => oVGA_H_SYNC~reg0.CLK
iCLK => V_Cont[9].CLK
iCLK => V_Cont[8].CLK
iCLK => V_Cont[7].CLK
iCLK => V_Cont[6].CLK
iCLK => V_Cont[5].CLK
iCLK => V_Cont[4].CLK
iCLK => V_Cont[3].CLK
iCLK => V_Cont[2].CLK
iCLK => V_Cont[1].CLK
iCLK => V_Cont[0].CLK
iCLK => oVGA_V_SYNC~reg0.CLK
iCLK => oVGA_CLOCK.DATAIN
iRST_N => oVGA_V_SYNC~reg0.ACLR
iRST_N => V_Cont[0].ACLR
iRST_N => V_Cont[1].ACLR
iRST_N => V_Cont[2].ACLR
iRST_N => V_Cont[3].ACLR
iRST_N => V_Cont[4].ACLR
iRST_N => V_Cont[5].ACLR
iRST_N => V_Cont[6].ACLR
iRST_N => V_Cont[7].ACLR
iRST_N => V_Cont[8].ACLR
iRST_N => V_Cont[9].ACLR
iRST_N => oVGA_H_SYNC~reg0.ACLR
iRST_N => H_Cont[0].ACLR
iRST_N => H_Cont[1].ACLR
iRST_N => H_Cont[2].ACLR
iRST_N => H_Cont[3].ACLR
iRST_N => H_Cont[4].ACLR
iRST_N => H_Cont[5].ACLR
iRST_N => H_Cont[6].ACLR
iRST_N => H_Cont[7].ACLR
iRST_N => H_Cont[8].ACLR
iRST_N => H_Cont[9].ACLR
iRST_N => oRequest~reg0.ACLR
iRST_N => oCoord_X[9]~reg0.ACLR
iRST_N => oCoord_X[8]~reg0.ACLR
iRST_N => oCoord_X[7]~reg0.ACLR
iRST_N => oCoord_X[6]~reg0.ACLR
iRST_N => oCoord_X[5]~reg0.ACLR
iRST_N => oCoord_X[4]~reg0.ACLR
iRST_N => oCoord_X[3]~reg0.ACLR
iRST_N => oCoord_X[2]~reg0.ACLR
iRST_N => oCoord_X[1]~reg0.ACLR
iRST_N => oCoord_X[0]~reg0.ACLR
iRST_N => oCoord_Y[9]~reg0.ACLR
iRST_N => oCoord_Y[8]~reg0.ACLR
iRST_N => oCoord_Y[7]~reg0.ACLR
iRST_N => oCoord_Y[6]~reg0.ACLR
iRST_N => oCoord_Y[5]~reg0.ACLR
iRST_N => oCoord_Y[4]~reg0.ACLR
iRST_N => oCoord_Y[3]~reg0.ACLR
iRST_N => oCoord_Y[2]~reg0.ACLR
iRST_N => oCoord_Y[1]~reg0.ACLR
iRST_N => oCoord_Y[0]~reg0.ACLR


|DE2_CCD_PIP|Reset_Delay:u2
iCLK => Cont[21].CLK
iCLK => Cont[20].CLK
iCLK => Cont[19].CLK
iCLK => Cont[18].CLK
iCLK => Cont[17].CLK
iCLK => Cont[16].CLK
iCLK => Cont[15].CLK
iCLK => Cont[14].CLK
iCLK => Cont[13].CLK
iCLK => Cont[12].CLK