de2_ccd_pip.hier_info

altera de2 开发板 vga lcd控制quatus 工程

|DE2_CCD_PIP
CLOCK_27 => CLOCK_27~0.IN1
CLOCK_50 => CLOCK_50~0.IN6
EXT_CLOCK => ~NO_FANOUT~
KEY[0] => KEY[0]~1.IN3
KEY[1] => KEY[1]~0.IN2
SW[0] => SW[0]~15.IN2
SW[1] => SW[1]~14.IN2
SW[2] => SW[2]~13.IN2
SW[3] => SW[3]~12.IN2
SW[4] => SW[4]~11.IN2
SW[5] => SW[5]~10.IN2
SW[6] => SW[6]~9.IN2
SW[7] => SW[7]~8.IN2
SW[8] => SW[8]~7.IN2
SW[9] => SW[9]~6.IN2
SW[10] => SW[10]~5.IN2
SW[11] => SW[11]~4.IN2
SW[12] => SW[12]~3.IN2
SW[13] => SW[13]~2.IN2
SW[14] => SW[14]~1.IN2
SW[15] => SW[15]~0.IN2
SW[16] => LEDR[16].DATAIN
SW[17] => LEDR[17].DATAIN
HEX0[0] <= SEG7_LUT_8:u5.oSEG0
HEX0[1] <= SEG7_LUT_8:u5.oSEG0
HEX0[2] <= SEG7_LUT_8:u5.oSEG0
HEX0[3] <= SEG7_LUT_8:u5.oSEG0
HEX0[4] <= SEG7_LUT_8:u5.oSEG0
HEX0[5] <= SEG7_LUT_8:u5.oSEG0
HEX0[6] <= SEG7_LUT_8:u5.oSEG0
HEX1[0] <= SEG7_LUT_8:u5.oSEG1
HEX1[1] <= SEG7_LUT_8:u5.oSEG1
HEX1[2] <= SEG7_LUT_8:u5.oSEG1
HEX1[3] <= SEG7_LUT_8:u5.oSEG1
HEX1[4] <= SEG7_LUT_8:u5.oSEG1
HEX1[5] <= SEG7_LUT_8:u5.oSEG1
HEX1[6] <= SEG7_LUT_8:u5.oSEG1
HEX2[0] <= SEG7_LUT_8:u5.oSEG2
HEX2[1] <= SEG7_LUT_8:u5.oSEG2
HEX2[2] <= SEG7_LUT_8:u5.oSEG2
HEX2[3] <= SEG7_LUT_8:u5.oSEG2
HEX2[4] <= SEG7_LUT_8:u5.oSEG2
HEX2[5] <= SEG7_LUT_8:u5.oSEG2
HEX2[6] <= SEG7_LUT_8:u5.oSEG2
HEX3[0] <= SEG7_LUT_8:u5.oSEG3
HEX3[1] <= SEG7_LUT_8:u5.oSEG3
HEX3[2] <= SEG7_LUT_8:u5.oSEG3
HEX3[3] <= SEG7_LUT_8:u5.oSEG3
HEX3[4] <= SEG7_LUT_8:u5.oSEG3
HEX3[5] <= SEG7_LUT_8:u5.oSEG3
HEX3[6] <= SEG7_LUT_8:u5.oSEG3
HEX4[0] <= SEG7_LUT_8:u5.oSEG4
HEX4[1] <= SEG7_LUT_8:u5.oSEG4
HEX4[2] <= SEG7_LUT_8:u5.oSEG4
HEX4[3] <= SEG7_LUT_8:u5.oSEG4
HEX4[4] <= SEG7_LUT_8:u5.oSEG4
HEX4[5] <= SEG7_LUT_8:u5.oSEG4
HEX4[6] <= SEG7_LUT_8:u5.oSEG4
HEX5[0] <= SEG7_LUT_8:u5.oSEG5
HEX5[1] <= SEG7_LUT_8:u5.oSEG5
HEX5[2] <= SEG7_LUT_8:u5.oSEG5
HEX5[3] <= SEG7_LUT_8:u5.oSEG5
HEX5[4] <= SEG7_LUT_8:u5.oSEG5
HEX5[5] <= SEG7_LUT_8:u5.oSEG5
HEX5[6] <= SEG7_LUT_8:u5.oSEG5
HEX6[0] <= SEG7_LUT_8:u5.oSEG6
HEX6[1] <= SEG7_LUT_8:u5.oSEG6
HEX6[2] <= SEG7_LUT_8:u5.oSEG6
HEX6[3] <= SEG7_LUT_8:u5.oSEG6
HEX6[4] <= SEG7_LUT_8:u5.oSEG6
HEX6[5] <= SEG7_LUT_8:u5.oSEG6
HEX6[6] <= SEG7_LUT_8:u5.oSEG6
HEX7[0] <= SEG7_LUT_8:u5.oSEG7
HEX7[1] <= SEG7_LUT_8:u5.oSEG7
HEX7[2] <= SEG7_LUT_8:u5.oSEG7
HEX7[3] <= SEG7_LUT_8:u5.oSEG7
HEX7[4] <= SEG7_LUT_8:u5.oSEG7
HEX7[5] <= SEG7_LUT_8:u5.oSEG7
HEX7[6] <= SEG7_LUT_8:u5.oSEG7
LEDG[0] <= Y1_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= Y1_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
LEDG[2] <= Y1_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
LEDG[3] <= Y1_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
LEDG[4] <= Y1_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
LEDG[5] <= Y1_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
LEDG[6] <= Y1_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
LEDG[7] <= Y1_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
LEDG[8] <= Y1_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
LEDR[0] <= SW[0]~15.DB_MAX_OUTPUT_PORT_TYPE
LEDR[1] <= SW[1]~14.DB_MAX_OUTPUT_PORT_TYPE
LEDR[2] <= SW[2]~13.DB_MAX_OUTPUT_PORT_TYPE
LEDR[3] <= SW[3]~12.DB_MAX_OUTPUT_PORT_TYPE
LEDR[4] <= SW[4]~11.DB_MAX_OUTPUT_PORT_TYPE
LEDR[5] <= SW[5]~10.DB_MAX_OUTPUT_PORT_TYPE
LEDR[6] <= SW[6]~9.DB_MAX_OUTPUT_PORT_TYPE
LEDR[7] <= SW[7]~8.DB_MAX_OUTPUT_PORT_TYPE
LEDR[8] <= SW[8]~7.DB_MAX_OUTPUT_PORT_TYPE
LEDR[9] <= SW[9]~6.DB_MAX_OUTPUT_PORT_TYPE
LEDR[10] <= SW[10]~5.DB_MAX_OUTPUT_PORT_TYPE
LEDR[11] <= SW[11]~4.DB_MAX_OUTPUT_PORT_TYPE
LEDR[12] <= SW[12]~3.DB_MAX_OUTPUT_PORT_TYPE
LEDR[13] <= SW[13]~2.DB_MAX_OUTPUT_PORT_TYPE
LEDR[14] <= SW[14]~1.DB_MAX_OUTPUT_PORT_TYPE
LEDR[15] <= SW[15]~0.DB_MAX_OUTPUT_PORT_TYPE
LEDR[16] <= SW[16].DB_MAX_OUTPUT_PORT_TYPE
LEDR[17] <= SW[17].DB_MAX_OUTPUT_PORT_TYPE
UART_TXD <= <GND>
UART_RXD => ~NO_FANOUT~
IRDA_TXD <= <GND>
IRDA_RXD => ~NO_FANOUT~
DRAM_DQ[0] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[1] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[2] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[3] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[4] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[5] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[6] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[7] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[8] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[9] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[10] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[11] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[12] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[13] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[14] <= Sdram_Control_8Port:u6.DQ
DRAM_DQ[15] <= Sdram_Control_8Port:u6.DQ
DRAM_ADDR[0] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[1] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[2] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[3] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[4] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[5] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[6] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[7] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[8] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[9] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[10] <= Sdram_Control_8Port:u6.SA
DRAM_ADDR[11] <= Sdram_Control_8Port:u6.SA
DRAM_LDQM <= Sdram_Control_8Port:u6.DQM
DRAM_UDQM <= Sdram_Control_8Port:u6.DQM
DRAM_WE_N <= Sdram_Control_8Port:u6.WE_N
DRAM_CAS_N <= Sdram_Control_8Port:u6.CAS_N
DRAM_RAS_N <= Sdram_Control_8Port:u6.RAS_N
DRAM_CS_N <= Sdram_Control_8Port:u6.CS_N
DRAM_BA_0 <= Sdram_Control_8Port:u6.BA
DRAM_BA_1 <= Sdram_Control_8Port:u6.BA
DRAM_CLK <= Sdram_Control_8Port:u6.SDR_CLK
DRAM_CKE <= Sdram_Control_8Port:u6.CKE
FL_DQ[0] <= FL_DQ[0]~0
FL_DQ[1] <= FL_DQ[1]~1
FL_DQ[2] <= FL_DQ[2]~2
FL_DQ[3] <= FL_DQ[3]~3
FL_DQ[4] <= FL_DQ[4]~4
FL_DQ[5] <= FL_DQ[5]~5
FL_DQ[6] <= FL_DQ[6]~6
FL_DQ[7] <= FL_DQ[7]~8
FL_ADDR[0] <= <GND>
FL_ADDR[1] <= <GND>
FL_ADDR[2] <= <GND>
FL_ADDR[3] <= <GND>
FL_ADDR[4] <= <GND>
FL_ADDR[5] <= <GND>
FL_ADDR[6] <= <GND>
FL_ADDR[7] <= <GND>
FL_ADDR[8] <= <GND>
FL_ADDR[9] <= <GND>
FL_ADDR[10] <= <GND>
FL_ADDR[11] <= <GND>
FL_ADDR[12] <= <GND>
FL_ADDR[13] <= <GND>
FL_ADDR[14] <= <GND>
FL_ADDR[15] <= <GND>
FL_ADDR[16] <= <GND>
FL_ADDR[17] <= <GND>
FL_ADDR[18] <= <GND>
FL_ADDR[19] <= <GND>
FL_ADDR[20] <= <GND>
FL_ADDR[21] <= <GND>
FL_WE_N <= <GND>
FL_RST_N <= <GND>
FL_OE_N <= <GND>
FL_CE_N <= <GND>
SRAM_DQ[0] <= SRAM_DQ[0]~0
SRAM_DQ[1] <= SRAM_DQ[1]~1
SRAM_DQ[2] <= SRAM_DQ[2]~2
SRAM_DQ[3] <= SRAM_DQ[3]~3
SRAM_DQ[4] <= SRAM_DQ[4]~4
SRAM_DQ[5] <= SRAM_DQ[5]~5
SRAM_DQ[6] <= SRAM_DQ[6]~6
SRAM_DQ[7] <= SRAM_DQ[7]~7
SRAM_DQ[8] <= SRAM_DQ[8]~8
SRAM_DQ[9] <= SRAM_DQ[9]~9
SRAM_DQ[10] <= SRAM_DQ[10]~10
SRAM_DQ[11] <= SRAM_DQ[11]~11
SRAM_DQ[12] <= SRAM_DQ[12]~12
SRAM_DQ[13] <= SRAM_DQ[13]~13
SRAM_DQ[14] <= SRAM_DQ[14]~14
SRAM_DQ[15] <= SRAM_DQ[15]~15
SRAM_ADDR[0] <= <GND>
SRAM_ADDR[1] <= <GND>
SRAM_ADDR[2] <= <GND>
SRAM_ADDR[3] <= <GND>
SRAM_ADDR[4] <= <GND>
SRAM_ADDR[5] <= <GND>
SRAM_ADDR[6] <= <GND>
SRAM_ADDR[7] <= <GND>
SRAM_ADDR[8] <= <GND>
SRAM_ADDR[9] <= <GND>
SRAM_ADDR[10] <= <GND>
SRAM_ADDR[11] <= <GND>
SRAM_ADDR[12] <= <GND>
SRAM_ADDR[13] <= <GND>
SRAM_ADDR[14] <= <GND>
SRAM_ADDR[15] <= <GND>
SRAM_ADDR[16] <= <GND>
SRAM_ADDR[17] <= <GND>
SRAM_UB_N <= <GND>
SRAM_LB_N <= <GND>
SRAM_WE_N <= <GND>
SRAM_CE_N <= <GND>
SRAM_OE_N <= <GND>
OTG_DATA[0] <= OTG_DATA[0]~0
OTG_DATA[1] <= OTG_DATA[1]~1
OTG_DATA[2] <= OTG_DATA[2]~2
OTG_DATA[3] <= OTG_DATA[3]~3
OTG_DATA[4] <= OTG_DATA[4]~4
OTG_DATA[5] <= OTG_DATA[5]~5
OTG_DATA[6] <= OTG_DATA[6]~6
OTG_DATA[7] <= OTG_DATA[7]~7
OTG_DATA[8] <= OTG_DATA[8]~8
OTG_DATA[9] <= OTG_DATA[9]~9
OTG_DATA[10] <= OTG_DATA[10]~10
OTG_DATA[11] <= OTG_DATA[11]~11
OTG_DATA[12] <= OTG_DATA[12]~12
OTG_DATA[13] <= OTG_DATA[13]~13
OTG_DATA[14] <= OTG_DATA[14]~14
OTG_DATA[15] <= OTG_DATA[15]~15
OTG_ADDR[0] <= <GND>
OTG_ADDR[1] <= <GND>
OTG_CS_N <= <GND>
OTG_RD_N <= <GND>
OTG_WR_N <= <GND>
OTG_RST_N <= <GND>
OTG_FSPEED <= <GND>
OTG_LSPEED <= <GND>
OTG_INT0 => ~NO_FANOUT~
OTG_INT1 => ~NO_FANOUT~
OTG_DREQ0 => ~NO_FANOUT~
OTG_DREQ1 => ~NO_FANOUT~
OTG_DACK0_N <= <GND>
OTG_DACK1_N <= <GND>
LCD_ON <= <VCC>
LCD_BLON <= <VCC>
LCD_RW <= <GND>
LCD_EN <= <GND>
LCD_RS <= <GND>
LCD_DATA[0] <= LCD_DATA[0]~0
LCD_DATA[1] <= LCD_DATA[1]~1
LCD_DATA[2] <= LCD_DATA[2]~2
LCD_DATA[3] <= LCD_DATA[3]~3
LCD_DATA[4] <= LCD_DATA[4]~4
LCD_DATA[5] <= LCD_DATA[5]~5
LCD_DATA[6] <= LCD_DATA[6]~6
LCD_DATA[7] <= LCD_DATA[7]~7
SD_DAT <= SD_DAT~0
SD_DAT3 <= <UNC>
SD_CMD <= <UNC>
SD_CLK <= <GND>
TDI => ~NO_FANOUT~
TCK => ~NO_FANOUT~
TCS => ~NO_FANOUT~
TDO <= <GND>
I2C_SDAT <= I2C_AV_Config:u10.I2C_SDAT
I2C_SDAT <= I2C_SDAT~0
I2C_SCLK <= I2C_AV_Config:u10.I2C_SCLK
PS2_DAT => ~NO_FANOUT~
PS2_CLK => ~NO_FANOUT~
VGA_CLK <= VGA_CTRL_CLK.DB_MAX_OUTPUT_PORT_TYPE
VGA_HS <= VGA_Controller:u1.oVGA_H_SYNC
VGA_VS <= VGA_Controller:u1.oVGA_V_SYNC
VGA_BLANK <= VGA_Controller:u1.oVGA_BLANK
VGA_SYNC <= VGA_Controller:u1.oVGA_SYNC
VGA_R[0] <= VGA_Controller:u1.oVGA_R
VGA_R[1] <= VGA_Controller:u1.oVGA_R
VGA_R[2] <= VGA_Controller:u1.oVGA_R
VGA_R[3] <= VGA_Controller:u1.oVGA_R
VGA_R[4] <= VGA_Controller:u1.oVGA_R
VGA_R[5] <= VGA_Controller:u1.oVGA_R
VGA_R[6] <= VGA_Controller:u1.oVGA_R
VGA_R[7] <= VGA_Controller:u1.oVGA_R
VGA_R[8] <= VGA_Controller:u1.oVGA_R
VGA_R[9] <= VGA_Controller:u1.oVGA_R
VGA_G[0] <= VGA_Controller:u1.oVGA_G
VGA_G[1] <= VGA_Controller:u1.oVGA_G
VGA_G[2] <= VGA_Controller:u1.oVGA_G
VGA_G[3] <= VGA_Controller:u1.oVGA_G
VGA_G[4] <= VGA_Controller:u1.oVGA_G
VGA_G[5] <= VGA_Controller:u1.oVGA_G
VGA_G[6] <= VGA_Controller:u1.oVGA_G
VGA_G[7] <= VGA_Controller:u1.oVGA_G
VGA_G[8] <= VGA_Controller:u1.oVGA_G
VGA_G[9] <= VGA_Controller:u1.oVGA_G
VGA_B[0] <= VGA_Controller:u1.oVGA_B
VGA_B[1] <= VGA_Controller:u1.oVGA_B
VGA_B[2] <= VGA_Controller:u1.oVGA_B
VGA_B[3] <= VGA_Controller:u1.oVGA_B
VGA_B[4] <= VGA_Controller:u1.oVGA_B
VGA_B[5] <= VGA_Controller:u1.oVGA_B
VGA_B[6] <= VGA_Controller:u1.oVGA_B
VGA_B[7] <= VGA_Controller:u1.oVGA_B
VGA_B[8] <= VGA_Controller:u1.oVGA_B
VGA_B[9] <= VGA_Controller:u1.oVGA_B
ENET_DATA[0] <= ENET_DATA[0]~0
ENET_DATA[1] <= ENET_DATA[1]~1
ENET_DATA[2] <= ENET_DATA[2]~2
ENET_DATA[3] <= ENET_DATA[3]~3
ENET_DATA[4] <= ENET_DATA[4]~4
ENET_DATA[5] <= ENET_DATA[5]~5
ENET_DATA[6] <= ENET_DATA[6]~6
ENET_DATA[7] <= ENET_DATA[7]~7
ENET_DATA[8] <= ENET_DATA[8]~8
ENET_DATA[9] <= ENET_DATA[9]~9
ENET_DATA[10] <= ENET_DATA[10]~10
ENET_DATA[11] <= ENET_DATA[11]~11
ENET_DATA[12] <= ENET_DATA[12]~12
ENET_DATA[13] <= ENET_DATA[13]~13
ENET_DATA[14] <= ENET_DATA[14]~14
ENET_DATA[15] <= ENET_DATA[15]~15
ENET_CMD <= <GND>
ENET_CS_N <= <GND>
ENET_WR_N <= <GND>
ENET_RD_N <= <GND>
ENET_RST_N <= <GND>
ENET_INT => ~NO_FANOUT~
ENET_CLK <= <GND>
AUD_ADCLRCK <= AUD_ADCLRCK~0
AUD_ADCDAT => ~NO_FANOUT~
AUD_DACLRCK <= AUD_DACLRCK~0
AUD_DACDAT <= <GND>
AUD_BCLK <= AUD_BCLK~0
AUD_XCK <= <GND>
TD_DATA[0] => ~NO_FANOUT~
TD_DATA[1] => ~NO_FANOUT~
TD_DATA[2] => ~NO_FANOUT~
TD_DATA[3] => ~NO_FANOUT~
TD_DATA[4] => ~NO_FANOUT~
TD_DATA[5] => ~NO_FANOUT~
TD_DATA[6] => ~NO_FANOUT~
TD_DATA[7] => ~NO_FANOUT~
TD_HS => ~NO_FANOUT~
TD_VS => ~NO_FANOUT~
TD_RESET <= <VCC>
GPIO_0[0] <= <UNC>
GPIO_0[1] <= <UNC>
GPIO_0[2] <= <UNC>
GPIO_0[3] <= <UNC>
GPIO_0[4] <= <UNC>
GPIO_0[5] <= <UNC>
GPIO_0[6] <= <UNC>
GPIO_0[7] <= <UNC>
GPIO_0[8] <= <UNC>
GPIO_0[9] <= <UNC>
GPIO_0[10] <= <UNC>
GPIO_0[11] <= <UNC>
GPIO_0[12] <= <UNC>
GPIO_0[13] <= <UNC>
GPIO_0[14] <= <UNC>
GPIO_0[15] <= <UNC>
GPIO_0[16] <= <UNC>
GPIO_0[17] <= <UNC>
GPIO_0[18] <= GPIO_0~16
GPIO_0[19] <= GPIO_0~17
GPIO_0[20] <= GPIO_0~18
GPIO_0[21] <= GPIO_0~19
GPIO_0[22] <= GPIO_0~20