de2_ccd_pip.hif

altera de2 开发板 vga lcd控制quatus 工程

PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
areset
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
d:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
d:|altera|72|quartus|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
d:|altera|72|quartus|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
d:|altera|72|quartus|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
control_interface
# storage
db|DE2_CCD_PIP.(19).cnf
db|DE2_CCD_PIP.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_8Port|control_interface.v
f269f46e0f3381c10fa32654c9c72f3
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
INIT_PER
24000
PARAMETER_SIGNED_DEC
DEF
REF_PER
1024
PARAMETER_SIGNED_DEC
DEF
SC_CL
3
PARAMETER_SIGNED_DEC
DEF
SC_RCD
3
PARAMETER_SIGNED_DEC
DEF
SC_RRD
7
PARAMETER_SIGNED_DEC
DEF
SC_PM
1
PARAMETER_SIGNED_DEC
DEF
SC_BL
1
PARAMETER_SIGNED_DEC
DEF
SDR_BL
111
PARAMETER_UNSIGNED_BIN
DEF
SDR_BT
0
PARAMETER_UNSIGNED_BIN
DEF
SDR_CL
011
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
Sdram_Control_8Port|Sdram_Params.h
f275caceb2982a5c6261a9748b135245
}
# hierarchies {
Sdram_Control_8Port:u6|control_interface:control1
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence
ASIZE23      ASIZE23      ASIZE23      
# end
# entity
command
# storage
db|DE2_CCD_PIP.(20).cnf
db|DE2_CCD_PIP.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_8Port|command.v
a7e807ca3959293dc31eb77e38aa3
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
INIT_PER
24000
PARAMETER_SIGNED_DEC
DEF
REF_PER
1024
PARAMETER_SIGNED_DEC
DEF
SC_CL
3
PARAMETER_SIGNED_DEC
DEF
SC_RCD
3
PARAMETER_SIGNED_DEC
DEF
SC_RRD
7
PARAMETER_SIGNED_DEC
DEF
SC_PM
1
PARAMETER_SIGNED_DEC
DEF
SC_BL
1
PARAMETER_SIGNED_DEC
DEF
SDR_BL
111
PARAMETER_UNSIGNED_BIN
DEF
SDR_BT
0
PARAMETER_UNSIGNED_BIN
DEF
SDR_CL
011
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
Sdram_Control_8Port|Sdram_Params.h
f275caceb2982a5c6261a9748b135245
}
# hierarchies {
Sdram_Control_8Port:u6|command:command1
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence
ASIZE23      ROWSIZE12COLSIZE8BANKSIZE2ROWSTART8          ROWSIZE12ROWSTART8          COLSTART0COLSIZE8COLSTART0BANKSTART20BANKSIZE2BANKSTART20ASIZE23      ASIZE23      
# end
# entity
sdr_data_path
# storage
db|DE2_CCD_PIP.(21).cnf
db|DE2_CCD_PIP.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_8Port|sdr_data_path.v
de752ab9c4558778f4e7459f1a713ee
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
INIT_PER
24000
PARAMETER_SIGNED_DEC
DEF
REF_PER
1024
PARAMETER_SIGNED_DEC
DEF
SC_CL
3
PARAMETER_SIGNED_DEC
DEF
SC_RCD
3
PARAMETER_SIGNED_DEC
DEF
SC_RRD
7
PARAMETER_SIGNED_DEC
DEF
SC_PM
1
PARAMETER_SIGNED_DEC
DEF
SC_BL
1
PARAMETER_SIGNED_DEC
DEF
SDR_BL
111
PARAMETER_UNSIGNED_BIN
DEF
SDR_BT
0
PARAMETER_UNSIGNED_BIN
DEF
SDR_CL
011
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
Sdram_Control_8Port|Sdram_Params.h
f275caceb2982a5c6261a9748b135245
}
# hierarchies {
Sdram_Control_8Port:u6|sdr_data_path:data_path1
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence
DSIZE16      DSIZE16      DSIZE16      DSIZE16      DSIZE16      DSIZE16      
# end
# entity
Sdram_WR_FIFO
# storage
db|DE2_CCD_PIP.(22).cnf
db|DE2_CCD_PIP.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_8Port|Sdram_WR_FIFO.v
6f86c12752ef275a4822c57ef66c1f2e
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
dcfifo
# storage
db|DE2_CCD_PIP.(23).cnf
db|DE2_CCD_PIP.(23).cnf
# case_insensitive
# source_file
d:|altera|72|quartus|libraries|megafunctions|dcfifo.tdf
3f8160e55eb1a7bff594d26d692f38
6
# user_parameter {
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
512
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
9
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_SIGNED_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_SIGNED_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
ADD_USEDW_MSB_BIT
OFF
PARAMETER_UNKNOWN
DEF
WRITE_ACLR_SYNCH
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
dcfifo_qlk1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrusedw
-1
3
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdusedw
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q
-1
3
data
-1
3
aclr
-1
3
}
# include_file {
d:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
d:|altera|72|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
d:|altera|72|quartus|libraries|megafunctions|lpm_counter.inc
7f888b135ddf66f0653c44cb18ac5
d:|altera|72|quartus|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
d:|altera|72|quartus|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
d:|altera|72|quartus|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
d:|altera|72|quartus|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
d:|altera|72|quartus|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
d:|altera|72|quartus|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
d:|altera|72|quartus|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
d:|altera|72|quartus|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
}
# hierarchies {
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
dcfifo_qlk1
# storage
db|DE2_CCD_PIP.(24).cnf
db|DE2_CCD_PIP.(24).cnf
# case_insensitive
# source_file
db|dcfifo_qlk1.tdf
7141b8514cc2f79d831858164aafebe
6
# used_port {
wrusedw8
-1
3
wrusedw7
-1
3
wrusedw6
-1
3
wrusedw5
-1
3
wrusedw4
-1
3
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdusedw8
-1
3
rdusedw7
-1
3
rdusedw6
-1
3
rdusedw5
-1
3
rdusedw4
-1
3
rdusedw3
-1
3
rdusedw2
-1
3
rdusedw1
-1
3
rdusedw0
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
aclr
-1
3
}
# hierarchies {
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
a_gray2bin_kdb
# storage
db|DE2_CCD_PIP.(25).cnf
db|DE2_CCD_PIP.(25).cnf
# case_insensitive
# source_file
db|a_gray2bin_kdb.tdf
e13f29541affcd7e421b4885669c911
6
# used_port {
gray9
-1
3
gray8
-1
3
gray7
-1
3
gray6
-1
3
gray5
-1
3
gray4
-1
3
gray3
-1
3
gray2
-1
3
gray1
-1
3
gray0
-1
3
bin9
-1
3
bin8
-1
3
bin7
-1
3
bin6
-1
3
bin5
-1
3
bin4
-1
3
bin3
-1
3
bin2
-1
3
bin1
-1
3
bin0
-1
3
}
# hierarchies {
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
a_graycounter_o96
# storage
db|DE2_CCD_PIP.(26).cnf
db|DE2_CCD_PIP.(26).cnf
# case_insensitive
# source_file
db|a_graycounter_o96.tdf
b7cb649354ec556e526a7bf35ea6ba
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
a_graycounter_fgc
# storage
db|DE2_CCD_PIP.(27).cnf
db|DE2_CCD_PIP.(27).cnf
# case_insensitive
# source_file
db|a_graycounter_fgc.tdf
ca8eeb5a7dc710b8caef78cac486f984
6
# used_port {
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
Sdram_Control_8Port:u6|Sdram_RD_FIFO