shift_taps_gkn.tdf

altera de2 开发板 vga lcd控制quatus 工程

--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" NUMBER_OF_TAPS=2 TAP_DISTANCE=1280 WIDTH=10 clken clock shiftin shiftout taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 7.2 cbx_altdpram 2007:04:25:14:55:30:SJ cbx_altshift_taps 2007:04:05:16:27:30:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_counter 2007:08:07:01:40:08:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


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FUNCTION altsyncram_4m81 (address_a[10..0], address_b[10..0], clock0, clocken0, data_a[19..0], wren_a)
RETURNS ( q_b[19..0]);
FUNCTION cntr_3rf (clk_en, clock)
RETURNS ( q[10..0]);

--synthesis_resources = lut 18 M4K 10 reg 11 
SUBDESIGN shift_taps_gkn
( 
	clken	:	input;
	clock	:	input;
	shiftin[9..0]	:	input;
	shiftout[9..0]	:	output;
	taps[19..0]	:	output;
) 
VARIABLE 
	altsyncram2 : altsyncram_4m81;
	cntr1 : cntr_3rf;

BEGIN 
	altsyncram2.address_a[] = cntr1.q[];
	altsyncram2.address_b[] = cntr1.q[];
	altsyncram2.clock0 = clock;
	altsyncram2.clocken0 = clken;
	altsyncram2.data_a[] = ( altsyncram2.q_b[9..0], shiftin[]);
	altsyncram2.wren_a = B"1";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	shiftout[9..0] = altsyncram2.q_b[19..10];
	taps[] = altsyncram2.q_b[];
END;
--VALID FILE