dffpipe_pe9.tdf

altera de2 开发板 vga lcd控制quatus 工程

--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 7.2 cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = reg 20 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_pe9
( 
	clock	:	input;
	clrn	:	input;
	d[9..0]	:	input;
	q[9..0]	:	output;
) 
VARIABLE 
	dffe8a[9..0] : dffe;
	dffe9a[9..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe8a[].clk = clock;
	dffe8a[].clrn = clrn;
	dffe8a[].d = (d[] & (! sclr));
	dffe8a[].ena = ena;
	dffe8a[].prn = prn;
	dffe9a[].clk = clock;
	dffe9a[].clrn = clrn;
	dffe9a[].d = (dffe8a[].q & (! sclr));
	dffe9a[].ena = ena;
	dffe9a[].prn = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe9a[].q;
	sclr = GND;
END;
--VALID FILE