de2_ccd_pip.map.qmsg

altera de2 开发板 vga lcd控制quatus 工程

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 LCM_Controller.v(132) " "Warning (10230): Verilog HDL assignment warning at LCM_Controller.v(132): truncated value with size 32 to match size of target (11)" {  } { { "LCM_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/LCM_Controller.v" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Controller VGA_Controller:u1 " "Info: Elaborating entity \"VGA_Controller\" for hierarchy \"VGA_Controller:u1\"" {  } { { "DE2_CCD_PIP.v" "u1" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/DE2_CCD_PIP.v" 507 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(58) " "Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(58): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/VGA_Controller.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(61) " "Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(61): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/VGA_Controller.v" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(64) " "Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(64): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/VGA_Controller.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(83) " "Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(83): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/VGA_Controller.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(84) " "Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(84): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/VGA_Controller.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(103) " "Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(103): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/VGA_Controller.v" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(129) " "Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(129): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/VGA_Controller.v" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:u2 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:u2\"" {  } { { "DE2_CCD_PIP.v" "u2" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/DE2_CCD_PIP.v" 513 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Reset_Delay.v(22) " "Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(22): truncated value with size 32 to match size of target (22)" {  } { { "Reset_Delay.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/Reset_Delay.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CCD_Capture CCD_Capture:u3 " "Info: Elaborating entity \"CCD_Capture\" for hierarchy \"CCD_Capture:u3\"" {  } { { "DE2_CCD_PIP.v" "u3" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/DE2_CCD_PIP.v" 526 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 CCD_Capture.v(79) " "Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(79): truncated value with size 32 to match size of target (11)" {  } { { "CCD_Capture.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/CCD_Capture.v" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 CCD_Capture.v(83) " "Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(83): truncated value with size 32 to match size of target (11)" {  } { { "CCD_Capture.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/CCD_Capture.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB_2X RAW2RGB_2X:u4 " "Info: Elaborating entity \"RAW2RGB_2X\" for hierarchy \"RAW2RGB_2X:u4\"" {  } { { "DE2_CCD_PIP.v" "u4" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/DE2_CCD_PIP.v" 550 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Line_Buffer RAW2RGB_2X:u4\|Line_Buffer:u0 " "Info: Elaborating entity \"Line_Buffer\" for hierarchy \"RAW2RGB_2X:u4\|Line_Buffer:u0\"" {  } { { "RAW2RGB_2X.v" "u0" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/RAW2RGB_2X.v" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift_taps " "Info: Found entity 1: altshift_taps" {  } { { "altshift_taps.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf" 45 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Info: Elaborating entity \"altshift_taps\" for hierarchy \"RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "Line_Buffer.v" "altshift_taps_component" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/Line_Buffer.v" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Info: Elaborated megafunction instantiation \"RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "Line_Buffer.v" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/Line_Buffer.v" 64 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_gkn.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/shift_taps_gkn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_gkn " "Info: Found entity 1: shift_taps_gkn" {  } { { "db/shift_taps_gkn.tdf" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/db/shift_taps_gkn.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_gkn RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated " "Info: Elaborating entity \"shift_taps_gkn\" for hierarchy \"RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf" 101 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4m81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4m81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4m81 " "Info: Found entity 1: altsyncram_4m81" {  } { { "db/altsyncram_4m81.tdf" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/db/altsyncram_4m81.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4m81 RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|altsyncram_4m81:altsyncram2 " "Info: Elaborating entity \"altsyncram_4m81\" for hierarchy \"RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|altsyncram_4m81:altsyncram2\"" {  } { { "db/shift_taps_gkn.tdf" "altsyncram2" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/db/shift_taps_gkn.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_3rf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_3rf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_3rf " "Info: Found entity 1: cntr_3rf" {  } { { "db/cntr_3rf.tdf" "" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/db/cntr_3rf.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_3rf RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|cntr_3rf:cntr1 " "Info: Elaborating entity \"cntr_3rf\" for hierarchy \"RAW2RGB_2X:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|cntr_3rf:cntr1\"" {  } { { "db/shift_taps_gkn.tdf" "cntr1" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/db/shift_taps_gkn.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB_4X RAW2RGB_4X:v4 " "Info: Elaborating entity \"RAW2RGB_4X\" for hierarchy \"RAW2RGB_4X:v4\"" {  } { { "DE2_CCD_PIP.v" "v4" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/DE2_CCD_PIP.v" 561 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 SEG7_LUT_8:u5 " "Info: Elaborating entity \"SEG7_LUT_8\" for hierarchy \"SEG7_LUT_8:u5\"" {  } { { "DE2_CCD_PIP.v" "u5" { Text "F:/development board/台湾开发板，vga，视频等/DE2/DE2_with_VGA_LCM/DE2_CCD_VGA_LCM/DE2_CCD_PIP.v" 567 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT_8:u5