de2_ccd_pip.tan.summary

altera de2 开发板 vga lcd控制quatus 工程

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.371 ns
From           : DRAM_DQ[8]
To             : Sdram_Control_8Port:u6|mDATAOUT[8]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.787 ns
From           : I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3]
To             : I2C_SCLK
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.830 ns
From           : SW[15]
To             : LEDR[15]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.681 ns
From           : SW[6]
To             : I2C_CCD_Config:u8|mI2C_DATA[6]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : -0.023 ns
Required Time  : 150.02 MHz ( period = 6.666 ns )
Actual Time    : 149.50 MHz ( period = 6.689 ns )
From           : Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|dffpipe_oe9:rs_bwp|dffe5a[0]
To             : Sdram_Control_8Port:u6|mADDR[17]
From Clock     : Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 1

Type           : Clock Setup: 'CLOCK_50'
Slack          : 7.050 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 169.49 MHz ( period = 5.900 ns )
From           : I2S_LCM_Config:u9|mI2S_DATA[12]
To             : I2S_LCM_Config:u9|I2S_Controller:u0|mSDATA
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'GPIO_1[10]'
Slack          : 33.665 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 157.85 MHz ( period = 6.335 ns )
From           : RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated|altsyncram_4m81:altsyncram2|q_b[10]
To             : RAW2RGB_2X:u4|mCCD_G[10]
From Clock     : GPIO_1[10]
To Clock       : GPIO_1[10]
Failed Paths   : 0

Type           : Clock Setup: 'GPIO_1[30]'
Slack          : 34.480 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 181.16 MHz ( period = 5.520 ns )
From           : RAW2RGB_4X:v4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated|altsyncram_4m81:altsyncram2|q_b[3]
To             : RAW2RGB_4X:v4|mCCD_G[10]
From Clock     : GPIO_1[30]
To Clock       : GPIO_1[30]
Failed Paths   : 0

Type           : Clock Setup: 'LCM_PLL:p0|altpll:altpll_component|_clk0'
Slack          : 48.066 ns
Required Time  : 18.41 MHz ( period = 54.320 ns )
Actual Time    : 159.90 MHz ( period = 6.254 ns )
From           : Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|rdptr_g[4]
To             : Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]
From Clock     : LCM_PLL:p0|altpll:altpll_component|_clk0
To Clock       : LCM_PLL:p0|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 150.02 MHz ( period = 6.666 ns )
Actual Time    : N/A
From           : Sdram_Control_8Port:u6|command:command1|oe4
To             : Sdram_Control_8Port:u6|command:command1|oe4
From Clock     : Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'LCM_PLL:p0|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 18.41 MHz ( period = 54.320 ns )
Actual Time    : N/A
From           : LCM_Controller:u0|mVGA_V_SYNC
To             : LCM_Controller:u0|mVGA_V_SYNC
From Clock     : LCM_PLL:p0|altpll:altpll_component|_clk0
To Clock       : LCM_PLL:p0|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'GPIO_1[10]'
Slack          : 0.391 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : CCD_Capture:u3|mCCD_FVAL
To             : CCD_Capture:u3|mCCD_FVAL
From Clock     : GPIO_1[10]
To Clock       : GPIO_1[10]
Failed Paths   : 0

Type           : Clock Hold: 'GPIO_1[30]'
Slack          : 0.391 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : CCD_Capture:v3|mCCD_FVAL
To             : CCD_Capture:v3|mCCD_FVAL
From Clock     : GPIO_1[30]
To Clock       : GPIO_1[30]
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : I2C_CCD_Config:u8|I2C_Controller:u0|SCLK
To             : I2C_CCD_Config:u8|I2C_Controller:u0|SCLK
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1

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