de2_ccd_pip.fit.rpt

altera de2 开发板 vga lcd控制quatus 工程

; Total pins                         ; 425 / 475 ( 89 % )                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 141,360 / 483,840 ( 29 % )               ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 2 / 4 ( 50 % )                           ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                 ; Setting                        ; Default Value                  ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                 ; EP2C35F672C6                   ;                                ;
; Fit Attempts to Skip                                   ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                            ; Off                            ; Off                            ;
; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                            ; Off                            ; Off                            ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Fitter Effort                                          ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                    ;
+--------------------------------------------+-----------------+------------------+--------------------------------+-----------+-------------------------------------------------------------------------------+------------------+
; Node                                       ; Action          ; Operation        ; Reason                         ; Node Port ; Destination Node                                                              ; Destination Port ;
+--------------------------------------------+-----------------+------------------+--------------------------------+-----------+-------------------------------------------------------------------------------+------------------+
; I2C_AV_Config:u10|I2C_Controller:u0|SD[0]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[15] ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[1]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[14] ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[2]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[13] ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[3]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[12] ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[4]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[11] ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[5]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[10] ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[6]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[9]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[7]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[8]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[8]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[7]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[9]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[6]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[10] ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[5]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[11] ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[4]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[12] ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[3]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[13] ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[2]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[14] ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[1]  ; PORTADATAOUT     ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD[15] ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ; I2C_AV_Config:u10|altsyncram:Ram0_rtl_0|altsyncram_cpv:auto_generated|q_a[0]  ; PORTADATAOUT     ;
; rCCD1_DATA[0]                              ; Packed Register ; Register Packing ; Fast Input Register assignment ; REGOUT    ; GPIO_1[0]                                                                     ; COMBOUT          ;
; rCCD1_DATA[1]                              ; Packed Register ; Register Packing ; Fast Input Register assignment ; REGOUT    ; GPIO_1[1]                                                                     ; COMBOUT          ;
; rCCD1_DATA[2]                              ; Packed Register ; Register Packing ; Fast Input Register assignment ; REGOUT    ; GPIO_1[5]                                                                     ; COMBOUT          ;
; rCCD1_DATA[3]                              ; Packed Register ; Register Packing ; Fast Input Register assignment ; REGOUT    ; GPIO_1[3]                                                                     ; COMBOUT          ;
; rCCD1_DATA[4]                              ; Packed Register ; Register Packing ; Fast Input Register assignment ; REGOUT    ; GPIO_1[2]                                                                     ; COMBOUT          ;