de2_ccd_pip.fit.rpt

altera de2 开发板 vga lcd控制quatus 工程

Fitter report for DE2_CCD_PIP
Wed Jan 31 11:02:37 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. Bidir Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. PLL Summary
 13. PLL Usage
 14. Clock Delay Control Summary
 15. Output Pin Default Load For Reported TCO
 16. Fitter Resource Utilization by Entity
 17. Delay Chain Summary
 18. Pad To Core Delay Chain Fanout
 19. Control Signals
 20. Global & Other Fast Signals
 21. Non-Global High Fan-Out Signals
 22. Fitter RAM Summary
 23. Interconnect Usage Summary
 24. LAB Logic Elements
 25. LAB-wide Signals
 26. LAB Signals Sourced
 27. LAB Signals Sourced Out
 28. LAB Distinct Inputs
 29. Fitter Device Options
 30. Fitter Messages
 31. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Fitter Summary                                                                ;
+------------------------------------+------------------------------------------+
; Fitter Status                      ; Successful - Wed Jan 31 11:02:36 2007    ;
; Quartus II Version                 ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name                      ; DE2_CCD_PIP                              ;
; Top-level Entity Name              ; DE2_CCD_PIP                              ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C35F672C6                             ;
; Timing Models                      ; Final                                    ;
; Total logic elements               ; 2,430 / 33,216 ( 7 % )                   ;
;     Total combinational functions  ; 1,937 / 33,216 ( 6 % )                   ;
;     Dedicated logic registers      ; 1,641 / 33,216 ( 5 % )                   ;
; Total registers                    ; 1665                                     ;