de2_ccd_pip.fit.smsg

altera de2 开发板 vga lcd控制quatus 工程

    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y13; Fanout = 1; REG Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|dffpipe_oe9:rs_bwp|dffe5a[0]'
    Info: 2: + IC(0.646 ns) + CELL(0.414 ns) = 1.060 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~138'
    Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.131 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~140'
    Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.202 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~142'
    Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.273 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~144'
    Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.344 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~146'
    Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.415 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~148'
    Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.486 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~150'
    Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.557 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~152'
    Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 1.967 ns; Loc. = LAB_X19_Y13; Fanout = 4; COMB Node = 'Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|op_1~153'
    Info: 11: + IC(1.835 ns) + CELL(0.275 ns) = 4.077 ns; Loc. = LAB_X31_Y20; Fanout = 23; COMB Node = 'Sdram_Control_8Port:u6|mADDR[16]~704'
    Info: 12: + IC(0.781 ns) + CELL(0.275 ns) = 5.133 ns; Loc. = LAB_X32_Y23; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|mADDR~757'
    Info: 13: + IC(0.290 ns) + CELL(0.271 ns) = 5.694 ns; Loc. = LAB_X32_Y23; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|mADDR~758'
    Info: 14: + IC(0.145 ns) + CELL(0.419 ns) = 6.258 ns; Loc. = LAB_X32_Y23; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|mADDR~759'
    Info: 15: + IC(0.290 ns) + CELL(0.271 ns) = 6.819 ns; Loc. = LAB_X32_Y23; Fanout = 1; COMB Node = 'Sdram_Control_8Port:u6|mADDR~760'
    Info: 16: + IC(0.397 ns) + CELL(0.084 ns) = 7.300 ns; Loc. = LAB_X32_Y23; Fanout = 1; REG Node = 'Sdram_Control_8Port:u6|mADDR[20]'
    Info: Total cell delay = 2.916 ns ( 39.95 % )
    Info: Total interconnect delay = 4.384 ns ( 60.05 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 11%
    Info: The peak interconnect region extends from location X22_Y12 to location X32_Y23
Info: Fitter routing operations ending: elapsed time is 00:00:12
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Fitter merged 8 physical RAM blocks that contain multiple logical RAM slices into a single location
    Info: Following physical RAM blocks contain multiple logical RAM slices
        Info: Physical RAM block M4K_X13_Y19 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a0
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a1
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a0
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a1
        Info: Physical RAM block M4K_X13_Y10 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a0
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a1
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a2
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a3
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a0
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a1
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a2
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a3
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a4
        Info: Physical RAM block M4K_X13_Y22 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a2
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a3
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a2
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a3
        Info: Physical RAM block M4K_X13_Y20 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a4
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a5
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a4
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a5
        Info: Physical RAM block M4K_X13_Y11 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a4
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a5
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a6
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a7
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a8
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a5
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a6
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a7
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a8
        Info: Physical RAM block M4K_X13_Y18 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a6
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a7
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a6
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a7
        Info: Physical RAM block M4K_X13_Y17 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a8
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a9
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a8
            Info: RAM slice: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated|ram_block1a9
        Info: Physical RAM block M4K_X13_Y9 contains the following logical RAM slices
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a9
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a0
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a1
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a2
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a3
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a5
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a6
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a7
            Info: RAM slice: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated|ram_block1a9
Info: Started post-fitting delay annotation
Warning: Found 377 output pins without output pin load capacitance assignment
    Info: Pin "HEX0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis