de2_ccd_pip.fit.smsg

altera de2 开发板 vga lcd控制quatus 工程

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Wed Jan 31 11:01:07 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_CCD_PIP -c DE2_CCD_PIP
Info: Selected device EP2C35F672C6 for design "DE2_CCD_PIP"
Info: Implemented PLL "Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll" as Cyclone II PLL type
    Info: Implementing clock multiplication of 3, clock division of 1, and phase shift of 0 degrees (0 ps) for Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 port
    Info: Implementing clock multiplication of 3, clock division of 1, and phase shift of -270 degrees (-5000 ps) for Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 port
Info: Implemented PLL "LCM_PLL:p0|altpll:altpll_component|pll" as Cyclone II PLL type
    Info: Implementing clock multiplication of 15, clock division of 22, and phase shift of 0 degrees (0 ps) for LCM_PLL:p0|altpll:altpll_component|_clk0 port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C50F672C6 is compatible
    Info: Device EP2C70F672C6 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location E3
    Info: Pin ~nCSO~ is reserved at location D3
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Automatically promoted node CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Promoted node GPIO_1[10]~21 
    Info: Promoted destinations to use location or clock signal Global Clock
Info: Pin GPIO_1[10] drives global or regional clock Global Clock, but is not placed in a dedicated clock pin position
Info: Promoted node GPIO_1[30]~5 
    Info: Promoted destinations to use location or clock signal Global Clock
Info: Pin GPIO_1[30] drives global or regional clock Global Clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted node LCM_PLL:p0|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_3)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11
Info: Automatically promoted node Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_1)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 (placed in counter C2 of PLL_1)
    Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X0_Y1_N1
Info: Automatically promoted node CCD2_MCLK 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node VGA_CLK
        Info: Destination node GPIO_1[11]
        Info: Destination node GPIO_1[31]
        Info: Destination node CCD2_MCLK~2
Info: Automatically promoted node I2C_CCD_Config:u8|mI2C_CTRL_CLK 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node I2C_CCD_Config:u7|I2C_Controller:u0|I2C_SCLK~255
        Info: Destination node I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~255
        Info: Destination node I2C_CCD_Config:u8|mI2C_CTRL_CLK~79
Info: Automatically promoted node I2C_AV_Config:u10|mI2C_CTRL_CLK 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~255
        Info: Destination node I2C_AV_Config:u10|mI2C_CTRL_CLK~79
Info: Automatically promoted node I2S_LCM_Config:u9|I2S_Controller:u0|mI2S_CLK 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node I2S_LCM_Config:u9|I2S_Controller:u0|I2S_CLK
        Info: Destination node I2S_LCM_Config:u9|I2S_Controller:u0|mI2S_CLK~77
Info: Automatically promoted node KEY[1] (placed in PIN N23 (LVDS126p, DPCLK7/DQS0R/CQ1R))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node I2C_CCD_Config:u7|mI2C_DATA[15]~964
        Info: Destination node I2C_CCD_Config:u8|mI2C_DATA[15]~964
        Info: Destination node I2C_CCD_Config:u7|I2C_Controller:u0|SD[15]~794
        Info: Destination node I2C_CCD_Config:u8|I2C_Controller:u0|SD[15]~794
Info: Automatically promoted node Reset_Delay:u2|oRST_0 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node Sdram_Control_8Port:u6|mWR~769
        Info: Destination node Reset_Delay:u2|oRST_0~31
        Info: Destination node Sdram_Control_8Port:u6|rWR2_ADDR[20]
        Info: Destination node Sdram_Control_8Port:u6|rWR3_ADDR[21]
        Info: Destination node Sdram_Control_8Port:u6|rRD2_ADDR[12]~1543
        Info: Destination node Sdram_Control_8Port:u6|rRD2_ADDR[12]~1546
        Info: Destination node Sdram_Control_8Port:u6|rWR1_ADDR[17]~1039
        Info: Destination node Sdram_Control_8Port:u6|rWR1_ADDR[17]~1042
        Info: Destination node Sdram_Control_8Port:u6|rWR4_ADDR[16]~1573
        Info: Destination node Sdram_Control_8Port:u6|rWR4_ADDR[16]~1577
        Info: Non-global destination nodes limited to 10 nodes
Info: Automatically promoted node Reset_Delay:u2|oRST_1 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node Reset_Delay:u2|oRST_1~54
Info: Automatically promoted node Reset_Delay:u2|oRST_2 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node Reset_Delay:u2|oRST_2~15
Info: Automatically promoted node Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|rdaclr 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|rdaclr 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_v9h1:auto_generated|rdaclr 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:03
    Extra Info: Packed 16 registers into blocks of type EC
    Extra Info: Packed 24 registers into blocks of type I/O
Warning: PLL "LCM_PLL:p0|altpll:altpll_component|pll" output port clk[0] feeds output pin "GPIO_0[29]" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:06
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:35
Info: Estimated most critical path is register to register delay of 7.300 ns