de2_ccd_pip.map.eqn

altera de2 开发板 vga lcd控制quatus 工程

--PB3_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[7]_PORT_A_data_in = VCC;
PB3_q_a[7]_PORT_A_data_in_reg = DFFE(PB3_q_a[7]_PORT_A_data_in, PB3_q_a[7]_clock_0, , , PB3_q_a[7]_clock_enable_0);
PB3_q_a[7]_PORT_B_data_in = J1_mDATAOUT[7];
PB3_q_a[7]_PORT_B_data_in_reg = DFFE(PB3_q_a[7]_PORT_B_data_in, PB3_q_a[7]_clock_1, , , PB3_q_a[7]_clock_enable_1);
PB3_q_a[7]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[7]_PORT_A_address_reg = DFFE(PB3_q_a[7]_PORT_A_address, PB3_q_a[7]_clock_0, , , PB3_q_a[7]_clock_enable_0);
PB3_q_a[7]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[7]_PORT_B_address_reg = DFFE(PB3_q_a[7]_PORT_B_address, PB3_q_a[7]_clock_1, , , PB3_q_a[7]_clock_enable_1);
PB3_q_a[7]_PORT_A_write_enable = GND;
PB3_q_a[7]_PORT_A_write_enable_reg = DFFE(PB3_q_a[7]_PORT_A_write_enable, PB3_q_a[7]_clock_0, , , PB3_q_a[7]_clock_enable_0);
PB3_q_a[7]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[7]_PORT_B_write_enable_reg = DFFE(PB3_q_a[7]_PORT_B_write_enable, PB3_q_a[7]_clock_1, , , PB3_q_a[7]_clock_enable_1);
PB3_q_a[7]_clock_0 = CCD1_MCLK;
PB3_q_a[7]_clock_1 = R2__clk0;
PB3_q_a[7]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[7]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[7]_clear_1 = !E1_oRST_0;
PB3_q_a[7]_PORT_A_data_out = MEMORY(PB3_q_a[7]_PORT_A_data_in_reg, PB3_q_a[7]_PORT_B_data_in_reg, PB3_q_a[7]_PORT_A_address_reg, PB3_q_a[7]_PORT_B_address_reg, PB3_q_a[7]_PORT_A_write_enable_reg, PB3_q_a[7]_PORT_B_write_enable_reg, , , PB3_q_a[7]_clock_0, PB3_q_a[7]_clock_1, PB3_q_a[7]_clock_enable_0, PB3_q_a[7]_clock_enable_1, , PB3_q_a[7]_clear_1);
PB3_q_a[7]_PORT_A_data_out_reg = DFFE(PB3_q_a[7]_PORT_A_data_out, PB3_q_a[7]_clock_0, PB3_q_a[7]_clear_1, , PB3_q_a[7]_clock_enable_0);
PB3_q_a[7] = PB3_q_a[7]_PORT_A_data_out_reg[0];


--D1L90 is VGA_Controller:u1|oVGA_G[2]~62
D1L90 = PB3_q_a[7] & D1L99 & D1L100;


--PB3_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[8]_PORT_A_data_in = VCC;
PB3_q_a[8]_PORT_A_data_in_reg = DFFE(PB3_q_a[8]_PORT_A_data_in, PB3_q_a[8]_clock_0, , , PB3_q_a[8]_clock_enable_0);
PB3_q_a[8]_PORT_B_data_in = J1_mDATAOUT[8];
PB3_q_a[8]_PORT_B_data_in_reg = DFFE(PB3_q_a[8]_PORT_B_data_in, PB3_q_a[8]_clock_1, , , PB3_q_a[8]_clock_enable_1);
PB3_q_a[8]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[8]_PORT_A_address_reg = DFFE(PB3_q_a[8]_PORT_A_address, PB3_q_a[8]_clock_0, , , PB3_q_a[8]_clock_enable_0);
PB3_q_a[8]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[8]_PORT_B_address_reg = DFFE(PB3_q_a[8]_PORT_B_address, PB3_q_a[8]_clock_1, , , PB3_q_a[8]_clock_enable_1);
PB3_q_a[8]_PORT_A_write_enable = GND;
PB3_q_a[8]_PORT_A_write_enable_reg = DFFE(PB3_q_a[8]_PORT_A_write_enable, PB3_q_a[8]_clock_0, , , PB3_q_a[8]_clock_enable_0);
PB3_q_a[8]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[8]_PORT_B_write_enable_reg = DFFE(PB3_q_a[8]_PORT_B_write_enable, PB3_q_a[8]_clock_1, , , PB3_q_a[8]_clock_enable_1);
PB3_q_a[8]_clock_0 = CCD1_MCLK;
PB3_q_a[8]_clock_1 = R2__clk0;
PB3_q_a[8]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[8]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[8]_clear_1 = !E1_oRST_0;
PB3_q_a[8]_PORT_A_data_out = MEMORY(PB3_q_a[8]_PORT_A_data_in_reg, PB3_q_a[8]_PORT_B_data_in_reg, PB3_q_a[8]_PORT_A_address_reg, PB3_q_a[8]_PORT_B_address_reg, PB3_q_a[8]_PORT_A_write_enable_reg, PB3_q_a[8]_PORT_B_write_enable_reg, , , PB3_q_a[8]_clock_0, PB3_q_a[8]_clock_1, PB3_q_a[8]_clock_enable_0, PB3_q_a[8]_clock_enable_1, , PB3_q_a[8]_clear_1);
PB3_q_a[8]_PORT_A_data_out_reg = DFFE(PB3_q_a[8]_PORT_A_data_out, PB3_q_a[8]_clock_0, PB3_q_a[8]_clear_1, , PB3_q_a[8]_clock_enable_0);
PB3_q_a[8] = PB3_q_a[8]_PORT_A_data_out_reg[0];


--D1L91 is VGA_Controller:u1|oVGA_G[3]~63
D1L91 = PB3_q_a[8] & D1L99 & D1L100;


--PB3_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[9]_PORT_A_data_in = VCC;
PB3_q_a[9]_PORT_A_data_in_reg = DFFE(PB3_q_a[9]_PORT_A_data_in, PB3_q_a[9]_clock_0, , , PB3_q_a[9]_clock_enable_0);
PB3_q_a[9]_PORT_B_data_in = J1_mDATAOUT[9];
PB3_q_a[9]_PORT_B_data_in_reg = DFFE(PB3_q_a[9]_PORT_B_data_in, PB3_q_a[9]_clock_1, , , PB3_q_a[9]_clock_enable_1);
PB3_q_a[9]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[9]_PORT_A_address_reg = DFFE(PB3_q_a[9]_PORT_A_address, PB3_q_a[9]_clock_0, , , PB3_q_a[9]_clock_enable_0);
PB3_q_a[9]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[9]_PORT_B_address_reg = DFFE(PB3_q_a[9]_PORT_B_address, PB3_q_a[9]_clock_1, , , PB3_q_a[9]_clock_enable_1);
PB3_q_a[9]_PORT_A_write_enable = GND;
PB3_q_a[9]_PORT_A_write_enable_reg = DFFE(PB3_q_a[9]_PORT_A_write_enable, PB3_q_a[9]_clock_0, , , PB3_q_a[9]_clock_enable_0);
PB3_q_a[9]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[9]_PORT_B_write_enable_reg = DFFE(PB3_q_a[9]_PORT_B_write_enable, PB3_q_a[9]_clock_1, , , PB3_q_a[9]_clock_enable_1);
PB3_q_a[9]_clock_0 = CCD1_MCLK;
PB3_q_a[9]_clock_1 = R2__clk0;
PB3_q_a[9]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[9]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[9]_clear_1 = !E1_oRST_0;
PB3_q_a[9]_PORT_A_data_out = MEMORY(PB3_q_a[9]_PORT_A_data_in_reg, PB3_q_a[9]_PORT_B_data_in_reg, PB3_q_a[9]_PORT_A_address_reg, PB3_q_a[9]_PORT_B_address_reg, PB3_q_a[9]_PORT_A_write_enable_reg, PB3_q_a[9]_PORT_B_write_enable_reg, , , PB3_q_a[9]_clock_0, PB3_q_a[9]_clock_1, PB3_q_a[9]_clock_enable_0, PB3_q_a[9]_clock_enable_1, , PB3_q_a[9]_clear_1);
PB3_q_a[9]_PORT_A_data_out_reg = DFFE(PB3_q_a[9]_PORT_A_data_out, PB3_q_a[9]_clock_0, PB3_q_a[9]_clear_1, , PB3_q_a[9]_clock_enable_0);
PB3_q_a[9] = PB3_q_a[9]_PORT_A_data_out_reg[0];


--D1L92 is VGA_Controller:u1|oVGA_G[4]~64
D1L92 = PB3_q_a[9] & D1L99 & D1L100;


--PB3_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[0]_PORT_A_data_in = VCC;
PB3_q_a[0]_PORT_A_data_in_reg = DFFE(PB3_q_a[0]_PORT_A_data_in, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_data_in = J1_mDATAOUT[0];
PB3_q_a[0]_PORT_B_data_in_reg = DFFE(PB3_q_a[0]_PORT_B_data_in, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[0]_PORT_A_address_reg = DFFE(PB3_q_a[0]_PORT_A_address, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[0]_PORT_B_address_reg = DFFE(PB3_q_a[0]_PORT_B_address, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_write_enable = GND;
PB3_q_a[0]_PORT_A_write_enable_reg = DFFE(PB3_q_a[0]_PORT_A_write_enable, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[0]_PORT_B_write_enable_reg = DFFE(PB3_q_a[0]_PORT_B_write_enable, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_clock_0 = CCD1_MCLK;
PB3_q_a[0]_clock_1 = R2__clk0;
PB3_q_a[0]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[0]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[0]_clear_1 = !E1_oRST_0;
PB3_q_a[0]_PORT_A_data_out = MEMORY(PB3_q_a[0]_PORT_A_data_in_reg, PB3_q_a[0]_PORT_B_data_in_reg, PB3_q_a[0]_PORT_A_address_reg, PB3_q_a[0]_PORT_B_address_reg, PB3_q_a[0]_PORT_A_write_enable_reg, PB3_q_a[0]_PORT_B_write_enable_reg, , , PB3_q_a[0]_clock_0, PB3_q_a[0]_clock_1, PB3_q_a[0]_clock_enable_0, PB3_q_a[0]_clock_enable_1, , PB3_q_a[0]_clear_1);
PB3_q_a[0]_PORT_A_data_out_reg = DFFE(PB3_q_a[0]_PORT_A_data_out, PB3_q_a[0]_clock_0, PB3_q_a[0]_clear_1, , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0] = PB3_q_a[0]_PORT_A_data_out_reg[0];


--D1L83 is VGA_Controller:u1|oVGA_B[0]~60
D1L83 = PB3_q_a[0] & D1L99 & D1L100;


--PB3_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[1]_PORT_A_data_in = VCC;
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = J1_mDATAOUT[1];
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = CCD1_MCLK;
PB3_q_a[1]_clock_1 = R2__clk0;
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !E1_oRST_0;
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1] = PB3_q_a[1]_PORT_A_data_out_reg[0];


--D1L84 is VGA_Controller:u1|oVGA_B[1]~61
D1L84 = PB3_q_a[1] & D1L99 & D1L100;


--PB3_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[2]_PORT_A_data_in = VCC;
PB3_q_a[2]_PORT_A_data_in_reg = DFFE(PB3_q_a[2]_PORT_A_data_in, PB3_q_a[2]_clock_0, , , PB3_q_a[2]_clock_enable_0);
PB3_q_a[2]_PORT_B_data_in = J1_mDATAOUT[2];
PB3_q_a[2]_PORT_B_data_in_reg = DFFE(PB3_q_a[2]_PORT_B_data_in, PB3_q_a[2]_clock_1, , , PB3_q_a[2]_clock_enable_1);
PB3_q_a[2]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[2]_PORT_A_address_reg = DFFE(PB3_q_a[2]_PORT_A_address, PB3_q_a[2]_clock_0, , , PB3_q_a[2]_clock_enable_0);
PB3_q_a[2]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[2]_PORT_B_address_reg = DFFE(PB3_q_a[2]_PORT_B_address, PB3_q_a[2]_clock_1, , , PB3_q_a[2]_clock_enable_1);
PB3_q_a[2]_PORT_A_write_enable = GND;
PB3_q_a[2]_PORT_A_write_enable_reg = DFFE(PB3_q_a[2]_PORT_A_write_enable, PB3_q_a[2]_clock_0, , , PB3_q_a[2]_clock_enable_0);
PB3_q_a[2]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[2]_PORT_B_write_enable_reg = DFFE(PB3_q_a[2]_PORT_B_write_enable, PB3_q_a[2]_clock_1, , , PB3_q_a[2]_clock_enable_1);
PB3_q_a[2]_clock_0 = CCD1_MCLK;
PB3_q_a[2]_clock_1 = R2__clk0;
PB3_q_a[2]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[2]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[2]_clear_1 = !E1_oRST_0;
PB3_q_a[2]_PORT_A_data_out = MEMORY(PB3_q_a[2]_PORT_A_data_in_reg, PB3_q_a[2]_PORT_B_data_in_reg, PB3_q_a[2]_PORT_A_address_reg, PB3_q_a[2]_PORT_B_address_reg, PB3_q_a[2]_PORT_A_write_enable_reg, PB3_q_a[2]_PORT_B_write_enable_reg, , , PB3_q_a[2]_clock_0, PB3_q_a[2]_clock_1, PB3_q_a[2]_clock_enable_0, PB3_q_a[2]_clock_enable_1, , PB3_q_a[2]_clear_1);
PB3_q_a[2]_PORT_A_data_out_reg = DFFE(PB3_q_a[2]_PORT_A_data_out, PB3_q_a[2]_clock_0, PB3_q_a[2]_clear_1, , PB3_q_a[2]_clock_enable_0);
PB3_q_a[2] = PB3_q_a[2]_PORT_A_data_out_reg[0];


--D1L85 is VGA_Controller:u1|oVGA_B[2]~62
D1L85 = PB3_q_a[2] & D1L99 & D1L100;


--PB3_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[3]_PORT_A_data_in = VCC;
PB3_q_a[3]_PORT_A_data_in_reg = DFFE(PB3_q_a[3]_PORT_A_data_in, PB3_q_a[3]_clock_0, , , PB3_q_a[3]_clock_enable_0);
PB3_q_a[3]_PORT_B_data_in = J1_mDATAOUT[3];
PB3_q_a[3]_PORT_B_data_in_reg = DFFE(PB3_q_a[3]_PORT_B_data_in, PB3_q_a[3]_clock_1, , , PB3_q_a[3]_clock_enable_1);
PB3_q_a[3]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[3]_PORT_A_address_reg = DFFE(PB3_q_a[3]_PORT_A_address, PB3_q_a[3]_clock_0, , , PB3_q_a[3]_clock_enable_0);
PB3_q_a[3]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[3]_PORT_B_address_reg = DFFE(PB3_q_a[3]_PORT_B_address, PB3_q_a[3]_clock_1, , , PB3_q_a[3]_clock_enable_1);
PB3_q_a[3]_PORT_A_write_enable = GND;
PB3_q_a[3]_PORT_A_write_enable_reg = DFFE(PB3_q_a[3]_PORT_A_write_enable, PB3_q_a[3]_clock_0, , , PB3_q_a[3]_clock_enable_0);
PB3_q_a[3]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[3]_PORT_B_write_enable_reg = DFFE(PB3_q_a[3]_PORT_B_write_enable, PB3_q_a[3]_clock_1, , , PB3_q_a[3]_clock_enable_1);
PB3_q_a[3]_clock_0 = CCD1_MCLK;
PB3_q_a[3]_clock_1 = R2__clk0;
PB3_q_a[3]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[3]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[3]_clear_1 = !E1_oRST_0;
PB3_q_a[3]_PORT_A_data_out = MEMORY(PB3_q_a[3]_PORT_A_data_in_reg, PB3_q_a[3]_PORT_B_data_in_reg, PB3_q_a[3]_PORT_A_address_reg, PB3_q_a[3]_PORT_B_address_reg, PB3_q_a[3]_PORT_A_write_enable_reg, PB3_q_a[3]_PORT_B_write_enable_reg, , , PB3_q_a[3]_clock_0, PB3_q_a[3]_clock_1, PB3_q_a[3]_clock_enable_0, PB3_q_a[3]_clock_enable_1, , PB3_q_a[3]_c