de2_ccd_pip.map.eqn

altera de2 开发板 vga lcd控制quatus 工程

D1_H_Cont[6] = DFFEAS(D1L27, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  , D1L46,  );


--D1L1 is VGA_Controller:u1|Equal~115
D1L1 = !D1_H_Cont[4] & !D1_H_Cont[5] & !D1_H_Cont[6];


--D1_H_Cont[7] is VGA_Controller:u1|H_Cont[7]
D1_H_Cont[7] = DFFEAS(D1L30, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  , D1L46,  );


--D1_H_Cont[8] is VGA_Controller:u1|H_Cont[8]
D1_H_Cont[8] = DFFEAS(D1L33, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  , D1L46,  );


--D1_H_Cont[9] is VGA_Controller:u1|H_Cont[9]
D1_H_Cont[9] = DFFEAS(D1L36, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  , D1L46,  );


--D1L100 is VGA_Controller:u1|oVGA_R~217
D1L100 = D1_H_Cont[8] & (D1L1 & !D1_H_Cont[7] # !D1_H_Cont[9]) # !D1_H_Cont[8] & (D1_H_Cont[9] # !D1L1 & D1_H_Cont[7]);


--D1L94 is VGA_Controller:u1|oVGA_R[0]~218
D1L94 = PB3_q_a[10] & D1L99 & D1L100;


--PB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[11]_PORT_A_data_in = VCC;
PB3_q_a[11]_PORT_A_data_in_reg = DFFE(PB3_q_a[11]_PORT_A_data_in, PB3_q_a[11]_clock_0, , , PB3_q_a[11]_clock_enable_0);
PB3_q_a[11]_PORT_B_data_in = J1_mDATAOUT[11];
PB3_q_a[11]_PORT_B_data_in_reg = DFFE(PB3_q_a[11]_PORT_B_data_in, PB3_q_a[11]_clock_1, , , PB3_q_a[11]_clock_enable_1);
PB3_q_a[11]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[11]_PORT_A_address_reg = DFFE(PB3_q_a[11]_PORT_A_address, PB3_q_a[11]_clock_0, , , PB3_q_a[11]_clock_enable_0);
PB3_q_a[11]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[11]_PORT_B_address_reg = DFFE(PB3_q_a[11]_PORT_B_address, PB3_q_a[11]_clock_1, , , PB3_q_a[11]_clock_enable_1);
PB3_q_a[11]_PORT_A_write_enable = GND;
PB3_q_a[11]_PORT_A_write_enable_reg = DFFE(PB3_q_a[11]_PORT_A_write_enable, PB3_q_a[11]_clock_0, , , PB3_q_a[11]_clock_enable_0);
PB3_q_a[11]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[11]_PORT_B_write_enable_reg = DFFE(PB3_q_a[11]_PORT_B_write_enable, PB3_q_a[11]_clock_1, , , PB3_q_a[11]_clock_enable_1);
PB3_q_a[11]_clock_0 = CCD1_MCLK;
PB3_q_a[11]_clock_1 = R2__clk0;
PB3_q_a[11]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[11]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[11]_clear_1 = !E1_oRST_0;
PB3_q_a[11]_PORT_A_data_out = MEMORY(PB3_q_a[11]_PORT_A_data_in_reg, PB3_q_a[11]_PORT_B_data_in_reg, PB3_q_a[11]_PORT_A_address_reg, PB3_q_a[11]_PORT_B_address_reg, PB3_q_a[11]_PORT_A_write_enable_reg, PB3_q_a[11]_PORT_B_write_enable_reg, , , PB3_q_a[11]_clock_0, PB3_q_a[11]_clock_1, PB3_q_a[11]_clock_enable_0, PB3_q_a[11]_clock_enable_1, , PB3_q_a[11]_clear_1);
PB3_q_a[11]_PORT_A_data_out_reg = DFFE(PB3_q_a[11]_PORT_A_data_out, PB3_q_a[11]_clock_0, PB3_q_a[11]_clear_1, , PB3_q_a[11]_clock_enable_0);
PB3_q_a[11] = PB3_q_a[11]_PORT_A_data_out_reg[0];


--D1L95 is VGA_Controller:u1|oVGA_R[1]~219
D1L95 = PB3_q_a[11] & D1L99 & D1L100;


--PB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[12]_PORT_A_data_in = VCC;
PB3_q_a[12]_PORT_A_data_in_reg = DFFE(PB3_q_a[12]_PORT_A_data_in, PB3_q_a[12]_clock_0, , , PB3_q_a[12]_clock_enable_0);
PB3_q_a[12]_PORT_B_data_in = J1_mDATAOUT[12];
PB3_q_a[12]_PORT_B_data_in_reg = DFFE(PB3_q_a[12]_PORT_B_data_in, PB3_q_a[12]_clock_1, , , PB3_q_a[12]_clock_enable_1);
PB3_q_a[12]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[12]_PORT_A_address_reg = DFFE(PB3_q_a[12]_PORT_A_address, PB3_q_a[12]_clock_0, , , PB3_q_a[12]_clock_enable_0);
PB3_q_a[12]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[12]_PORT_B_address_reg = DFFE(PB3_q_a[12]_PORT_B_address, PB3_q_a[12]_clock_1, , , PB3_q_a[12]_clock_enable_1);
PB3_q_a[12]_PORT_A_write_enable = GND;
PB3_q_a[12]_PORT_A_write_enable_reg = DFFE(PB3_q_a[12]_PORT_A_write_enable, PB3_q_a[12]_clock_0, , , PB3_q_a[12]_clock_enable_0);
PB3_q_a[12]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[12]_PORT_B_write_enable_reg = DFFE(PB3_q_a[12]_PORT_B_write_enable, PB3_q_a[12]_clock_1, , , PB3_q_a[12]_clock_enable_1);
PB3_q_a[12]_clock_0 = CCD1_MCLK;
PB3_q_a[12]_clock_1 = R2__clk0;
PB3_q_a[12]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[12]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[12]_clear_1 = !E1_oRST_0;
PB3_q_a[12]_PORT_A_data_out = MEMORY(PB3_q_a[12]_PORT_A_data_in_reg, PB3_q_a[12]_PORT_B_data_in_reg, PB3_q_a[12]_PORT_A_address_reg, PB3_q_a[12]_PORT_B_address_reg, PB3_q_a[12]_PORT_A_write_enable_reg, PB3_q_a[12]_PORT_B_write_enable_reg, , , PB3_q_a[12]_clock_0, PB3_q_a[12]_clock_1, PB3_q_a[12]_clock_enable_0, PB3_q_a[12]_clock_enable_1, , PB3_q_a[12]_clear_1);
PB3_q_a[12]_PORT_A_data_out_reg = DFFE(PB3_q_a[12]_PORT_A_data_out, PB3_q_a[12]_clock_0, PB3_q_a[12]_clear_1, , PB3_q_a[12]_clock_enable_0);
PB3_q_a[12] = PB3_q_a[12]_PORT_A_data_out_reg[0];


--D1L96 is VGA_Controller:u1|oVGA_R[2]~220
D1L96 = PB3_q_a[12] & D1L99 & D1L100;


--PB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[13]_PORT_A_data_in = VCC;
PB3_q_a[13]_PORT_A_data_in_reg = DFFE(PB3_q_a[13]_PORT_A_data_in, PB3_q_a[13]_clock_0, , , PB3_q_a[13]_clock_enable_0);
PB3_q_a[13]_PORT_B_data_in = J1_mDATAOUT[13];
PB3_q_a[13]_PORT_B_data_in_reg = DFFE(PB3_q_a[13]_PORT_B_data_in, PB3_q_a[13]_clock_1, , , PB3_q_a[13]_clock_enable_1);
PB3_q_a[13]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[13]_PORT_A_address_reg = DFFE(PB3_q_a[13]_PORT_A_address, PB3_q_a[13]_clock_0, , , PB3_q_a[13]_clock_enable_0);
PB3_q_a[13]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[13]_PORT_B_address_reg = DFFE(PB3_q_a[13]_PORT_B_address, PB3_q_a[13]_clock_1, , , PB3_q_a[13]_clock_enable_1);
PB3_q_a[13]_PORT_A_write_enable = GND;
PB3_q_a[13]_PORT_A_write_enable_reg = DFFE(PB3_q_a[13]_PORT_A_write_enable, PB3_q_a[13]_clock_0, , , PB3_q_a[13]_clock_enable_0);
PB3_q_a[13]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[13]_PORT_B_write_enable_reg = DFFE(PB3_q_a[13]_PORT_B_write_enable, PB3_q_a[13]_clock_1, , , PB3_q_a[13]_clock_enable_1);
PB3_q_a[13]_clock_0 = CCD1_MCLK;
PB3_q_a[13]_clock_1 = R2__clk0;
PB3_q_a[13]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[13]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[13]_clear_1 = !E1_oRST_0;
PB3_q_a[13]_PORT_A_data_out = MEMORY(PB3_q_a[13]_PORT_A_data_in_reg, PB3_q_a[13]_PORT_B_data_in_reg, PB3_q_a[13]_PORT_A_address_reg, PB3_q_a[13]_PORT_B_address_reg, PB3_q_a[13]_PORT_A_write_enable_reg, PB3_q_a[13]_PORT_B_write_enable_reg, , , PB3_q_a[13]_clock_0, PB3_q_a[13]_clock_1, PB3_q_a[13]_clock_enable_0, PB3_q_a[13]_clock_enable_1, , PB3_q_a[13]_clear_1);
PB3_q_a[13]_PORT_A_data_out_reg = DFFE(PB3_q_a[13]_PORT_A_data_out, PB3_q_a[13]_clock_0, PB3_q_a[13]_clear_1, , PB3_q_a[13]_clock_enable_0);
PB3_q_a[13] = PB3_q_a[13]_PORT_A_data_out_reg[0];


--D1L97 is VGA_Controller:u1|oVGA_R[3]~221
D1L97 = PB3_q_a[13] & D1L99 & D1L100;


--PB3_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[14]_PORT_A_data_in = VCC;
PB3_q_a[14]_PORT_A_data_in_reg = DFFE(PB3_q_a[14]_PORT_A_data_in, PB3_q_a[14]_clock_0, , , PB3_q_a[14]_clock_enable_0);
PB3_q_a[14]_PORT_B_data_in = J1_mDATAOUT[14];
PB3_q_a[14]_PORT_B_data_in_reg = DFFE(PB3_q_a[14]_PORT_B_data_in, PB3_q_a[14]_clock_1, , , PB3_q_a[14]_clock_enable_1);
PB3_q_a[14]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[14]_PORT_A_address_reg = DFFE(PB3_q_a[14]_PORT_A_address, PB3_q_a[14]_clock_0, , , PB3_q_a[14]_clock_enable_0);
PB3_q_a[14]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[14]_PORT_B_address_reg = DFFE(PB3_q_a[14]_PORT_B_address, PB3_q_a[14]_clock_1, , , PB3_q_a[14]_clock_enable_1);
PB3_q_a[14]_PORT_A_write_enable = GND;
PB3_q_a[14]_PORT_A_write_enable_reg = DFFE(PB3_q_a[14]_PORT_A_write_enable, PB3_q_a[14]_clock_0, , , PB3_q_a[14]_clock_enable_0);
PB3_q_a[14]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[14]_PORT_B_write_enable_reg = DFFE(PB3_q_a[14]_PORT_B_write_enable, PB3_q_a[14]_clock_1, , , PB3_q_a[14]_clock_enable_1);
PB3_q_a[14]_clock_0 = CCD1_MCLK;
PB3_q_a[14]_clock_1 = R2__clk0;
PB3_q_a[14]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[14]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[14]_clear_1 = !E1_oRST_0;
PB3_q_a[14]_PORT_A_data_out = MEMORY(PB3_q_a[14]_PORT_A_data_in_reg, PB3_q_a[14]_PORT_B_data_in_reg, PB3_q_a[14]_PORT_A_address_reg, PB3_q_a[14]_PORT_B_address_reg, PB3_q_a[14]_PORT_A_write_enable_reg, PB3_q_a[14]_PORT_B_write_enable_reg, , , PB3_q_a[14]_clock_0, PB3_q_a[14]_clock_1, PB3_q_a[14]_clock_enable_0, PB3_q_a[14]_clock_enable_1, , PB3_q_a[14]_clear_1);
PB3_q_a[14]_PORT_A_data_out_reg = DFFE(PB3_q_a[14]_PORT_A_data_out, PB3_q_a[14]_clock_0, PB3_q_a[14]_clear_1, , PB3_q_a[14]_clock_enable_0);
PB3_q_a[14] = PB3_q_a[14]_PORT_A_data_out_reg[0];


--D1L98 is VGA_Controller:u1|oVGA_R[4]~222
D1L98 = PB3_q_a[14] & D1L99 & D1L100;


--PB3_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[5]_PORT_A_data_in = VCC;
PB3_q_a[5]_PORT_A_data_in_reg = DFFE(PB3_q_a[5]_PORT_A_data_in, PB3_q_a[5]_clock_0, , , PB3_q_a[5]_clock_enable_0);
PB3_q_a[5]_PORT_B_data_in = J1_mDATAOUT[5];
PB3_q_a[5]_PORT_B_data_in_reg = DFFE(PB3_q_a[5]_PORT_B_data_in, PB3_q_a[5]_clock_1, , , PB3_q_a[5]_clock_enable_1);
PB3_q_a[5]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[5]_PORT_A_address_reg = DFFE(PB3_q_a[5]_PORT_A_address, PB3_q_a[5]_clock_0, , , PB3_q_a[5]_clock_enable_0);
PB3_q_a[5]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[5]_PORT_B_address_reg = DFFE(PB3_q_a[5]_PORT_B_address, PB3_q_a[5]_clock_1, , , PB3_q_a[5]_clock_enable_1);
PB3_q_a[5]_PORT_A_write_enable = GND;
PB3_q_a[5]_PORT_A_write_enable_reg = DFFE(PB3_q_a[5]_PORT_A_write_enable, PB3_q_a[5]_clock_0, , , PB3_q_a[5]_clock_enable_0);
PB3_q_a[5]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[5]_PORT_B_write_enable_reg = DFFE(PB3_q_a[5]_PORT_B_write_enable, PB3_q_a[5]_clock_1, , , PB3_q_a[5]_clock_enable_1);
PB3_q_a[5]_clock_0 = CCD1_MCLK;
PB3_q_a[5]_clock_1 = R2__clk0;
PB3_q_a[5]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[5]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[5]_clear_1 = !E1_oRST_0;
PB3_q_a[5]_PORT_A_data_out = MEMORY(PB3_q_a[5]_PORT_A_data_in_reg, PB3_q_a[5]_PORT_B_data_in_reg, PB3_q_a[5]_PORT_A_address_reg, PB3_q_a[5]_PORT_B_address_reg, PB3_q_a[5]_PORT_A_write_enable_reg, PB3_q_a[5]_PORT_B_write_enable_reg, , , PB3_q_a[5]_clock_0, PB3_q_a[5]_clock_1, PB3_q_a[5]_clock_enable_0, PB3_q_a[5]_clock_enable_1, , PB3_q_a[5]_clear_1);
PB3_q_a[5]_PORT_A_data_out_reg = DFFE(PB3_q_a[5]_PORT_A_data_out, PB3_q_a[5]_clock_0, PB3_q_a[5]_clear_1, , PB3_q_a[5]_clock_enable_0);
PB3_q_a[5] = PB3_q_a[5]_PORT_A_data_out_reg[0];


--D1L88 is VGA_Controller:u1|oVGA_G[0]~60
D1L88 = PB3_q_a[5] & D1L99 & D1L100;


--PB3_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[6]_PORT_A_data_in = VCC;
PB3_q_a[6]_PORT_A_data_in_reg = DFFE(PB3_q_a[6]_PORT_A_data_in, PB3_q_a[6]_clock_0, , , PB3_q_a[6]_clock_enable_0);
PB3_q_a[6]_PORT_B_data_in = J1_mDATAOUT[6];
PB3_q_a[6]_PORT_B_data_in_reg = DFFE(PB3_q_a[6]_PORT_B_data_in, PB3_q_a[6]_clock_1, , , PB3_q_a[6]_clock_enable_1);
PB3_q_a[6]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[6]_PORT_A_address_reg = DFFE(PB3_q_a[6]_PORT_A_address, PB3_q_a[6]_clock_0, , , PB3_q_a[6]_clock_enable_0);
PB3_q_a[6]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[6]_PORT_B_address_reg = DFFE(PB3_q_a[6]_PORT_B_address, PB3_q_a[6]_clock_1, , , PB3_q_a[6]_clock_enable_1);
PB3_q_a[6]_PORT_A_write_enable = GND;
PB3_q_a[6]_PORT_A_write_enable_reg = DFFE(PB3_q_a[6]_PORT_A_write_enable, PB3_q_a[6]_clock_0, , , PB3_q_a[6]_clock_enable_0);
PB3_q_a[6]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[6]_PORT_B_write_enable_reg = DFFE(PB3_q_a[6]_PORT_B_write_enable, PB3_q_a[6]_clock_1, , , PB3_q_a[6]_clock_enable_1);
PB3_q_a[6]_clock_0 = CCD1_MCLK;
PB3_q_a[6]_clock_1 = R2__clk0;
PB3_q_a[6]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[6]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[6]_clear_1 = !E1_oRST_0;
PB3_q_a[6]_PORT_A_data_out = MEMORY(PB3_q_a[6]_PORT_A_data_in_reg, PB3_q_a[6]_PORT_B_data_in_reg, PB3_q_a[6]_PORT_A_address_reg, PB3_q_a[6]_PORT_B_address_reg, PB3_q_a[6]_PORT_A_write_enable_reg, PB3_q_a[6]_PORT_B_write_enable_reg, , , PB3_q_a[6]_clock_0, PB3_q_a[6]_clock_1, PB3_q_a[6]_clock_enable_0, PB3_q_a[6]_clock_enable_1, , PB3_q_a[6]_clear_1);
PB3_q_a[6]_PORT_A_data_out_reg = DFFE(PB3_q_a[6]_PORT_A_data_out, PB3_q_a[6]_clock_0, PB3_q_a[6]_clear_1, , PB3_q_a[6]_clock_enable_0);
PB3_q_a[6] = PB3_q_a[6]_PORT_A_data_out_reg[0];


--D1L89 is VGA_Controller:u1|oVGA_G[1]~61
D1L89 = PB3_q_a[6] & D1L99 & D1L100;