de2_ccd_pip.map.eqn

altera de2 开发板 vga lcd控制quatus 工程

--J1_SA[6] is Sdram_Control_4Port:u6|SA[6]
J1_SA[6] = DFFEAS(J1L83, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_SA[7] is Sdram_Control_4Port:u6|SA[7]
J1_SA[7] = DFFEAS(J1L84, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_SA[8] is Sdram_Control_4Port:u6|SA[8]
J1_SA[8] = DFFEAS(J1L85, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_SA[9] is Sdram_Control_4Port:u6|SA[9]
J1_SA[9] = DFFEAS(J1L86, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_SA[10] is Sdram_Control_4Port:u6|SA[10]
J1_SA[10] = DFFEAS(J1L87, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_SA[11] is Sdram_Control_4Port:u6|SA[11]
J1_SA[11] = DFFEAS(J1L88, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_DQM[1] is Sdram_Control_4Port:u6|DQM[1]
J1_DQM[1] = DFFEAS(J1L14, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_WE_N is Sdram_Control_4Port:u6|WE_N
J1_WE_N = DFFEAS(J1L117, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_CAS_N is Sdram_Control_4Port:u6|CAS_N
J1_CAS_N = DFFEAS(J1L5, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_RAS_N is Sdram_Control_4Port:u6|RAS_N
J1_RAS_N = DFFEAS(J1L50, R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_CS_N[0] is Sdram_Control_4Port:u6|CS_N[0]
J1_CS_N[0] = DFFEAS(Y1_CS_N[0], R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_BA[0] is Sdram_Control_4Port:u6|BA[0]
J1_BA[0] = DFFEAS(Y1_BA[0], R2__clk0,  ,  ,  ,  ,  ,  ,  );


--J1_BA[1] is Sdram_Control_4Port:u6|BA[1]
J1_BA[1] = DFFEAS(Y1_BA[1], R2__clk0,  ,  ,  ,  ,  ,  ,  );


--R2__clk0 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
R2__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());

--R2__clk1 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1
R2__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());


--SB3L47Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[0]~reg0
SB3L47Q = DFFEAS(SB3L45, M1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !M1_mI2C_GO);


--SB3L53Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[2]~reg0
SB3L53Q = DFFEAS(SB3L51, M1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !M1_mI2C_GO);


--SB3L56Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3]~reg0
SB3L56Q = DFFEAS(SB3L54, M1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !M1_mI2C_GO);


--SB3L50Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[1]~reg0
SB3L50Q = DFFEAS(SB3L48, M1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !M1_mI2C_GO);


--SB3L15 is I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~253
SB3L15 = SB3L47Q # SB3L53Q # SB3L56Q # SB3L50Q;


--SB3L59Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[4]~reg0
SB3L59Q = DFFEAS(SB3L57, M1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !M1_mI2C_GO);


--SB3L16 is I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~254
SB3L16 = SB3L59Q & (!SB3L56Q # !SB3L53Q) # !SB3L59Q & SB3L15;


--SB3L62Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[5]~reg0
SB3L62Q = DFFEAS(SB3L60, M1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !M1_mI2C_GO);


--M1_mI2C_CTRL_CLK is I2C_AV_Config:u10|mI2C_CTRL_CLK
M1_mI2C_CTRL_CLK = DFFEAS(M1L80, CLOCK_50, KEY[0],  ,  ,  ,  ,  ,  );


--SB3_SCLK is I2C_AV_Config:u10|I2C_Controller:u0|SCLK
SB3_SCLK = DFFEAS(SB3L23, M1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--SB3L17 is I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~255
SB3L17 = SB3L16 & SB3L62Q & !M1_mI2C_CTRL_CLK # !SB3_SCLK;


--CCD1_MCLK is CCD1_MCLK
CCD1_MCLK = DFFEAS(A1L8, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--D1_oVGA_H_SYNC is VGA_Controller:u1|oVGA_H_SYNC
D1_oVGA_H_SYNC = DFFEAS(D1L42, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  ,  ,  );


--D1_oVGA_V_SYNC is VGA_Controller:u1|oVGA_V_SYNC
D1_oVGA_V_SYNC = DFFEAS(D1L102, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  ,  ,  );


--D1_oVGA_BLANK is VGA_Controller:u1|oVGA_BLANK
D1_oVGA_BLANK = D1_oVGA_H_SYNC & D1_oVGA_V_SYNC;


--PB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[10]_PORT_A_data_in = VCC;
PB3_q_a[10]_PORT_A_data_in_reg = DFFE(PB3_q_a[10]_PORT_A_data_in, PB3_q_a[10]_clock_0, , , PB3_q_a[10]_clock_enable_0);
PB3_q_a[10]_PORT_B_data_in = J1_mDATAOUT[10];
PB3_q_a[10]_PORT_B_data_in_reg = DFFE(PB3_q_a[10]_PORT_B_data_in, PB3_q_a[10]_clock_1, , , PB3_q_a[10]_clock_enable_1);
PB3_q_a[10]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[10]_PORT_A_address_reg = DFFE(PB3_q_a[10]_PORT_A_address, PB3_q_a[10]_clock_0, , , PB3_q_a[10]_clock_enable_0);
PB3_q_a[10]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[10]_PORT_B_address_reg = DFFE(PB3_q_a[10]_PORT_B_address, PB3_q_a[10]_clock_1, , , PB3_q_a[10]_clock_enable_1);
PB3_q_a[10]_PORT_A_write_enable = GND;
PB3_q_a[10]_PORT_A_write_enable_reg = DFFE(PB3_q_a[10]_PORT_A_write_enable, PB3_q_a[10]_clock_0, , , PB3_q_a[10]_clock_enable_0);
PB3_q_a[10]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[10]_PORT_B_write_enable_reg = DFFE(PB3_q_a[10]_PORT_B_write_enable, PB3_q_a[10]_clock_1, , , PB3_q_a[10]_clock_enable_1);
PB3_q_a[10]_clock_0 = CCD1_MCLK;
PB3_q_a[10]_clock_1 = R2__clk0;
PB3_q_a[10]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[10]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[10]_clear_1 = !E1_oRST_0;
PB3_q_a[10]_PORT_A_data_out = MEMORY(PB3_q_a[10]_PORT_A_data_in_reg, PB3_q_a[10]_PORT_B_data_in_reg, PB3_q_a[10]_PORT_A_address_reg, PB3_q_a[10]_PORT_B_address_reg, PB3_q_a[10]_PORT_A_write_enable_reg, PB3_q_a[10]_PORT_B_write_enable_reg, , , PB3_q_a[10]_clock_0, PB3_q_a[10]_clock_1, PB3_q_a[10]_clock_enable_0, PB3_q_a[10]_clock_enable_1, , PB3_q_a[10]_clear_1);
PB3_q_a[10]_PORT_A_data_out_reg = DFFE(PB3_q_a[10]_PORT_A_data_out, PB3_q_a[10]_clock_0, PB3_q_a[10]_clear_1, , PB3_q_a[10]_clock_enable_0);
PB3_q_a[10] = PB3_q_a[10]_PORT_A_data_out_reg[0];


--D1_V_Cont[6] is VGA_Controller:u1|V_Cont[6]
D1_V_Cont[6] = DFFEAS(D1L68, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1_V_Cont[7] is VGA_Controller:u1|V_Cont[7]
D1_V_Cont[7] = DFFEAS(D1L71, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1_V_Cont[8] is VGA_Controller:u1|V_Cont[8]
D1_V_Cont[8] = DFFEAS(D1L74, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1L38 is VGA_Controller:u1|LessThan~1087
D1L38 = !D1_V_Cont[6] & !D1_V_Cont[7] & !D1_V_Cont[8];


--D1_V_Cont[1] is VGA_Controller:u1|V_Cont[1]
D1_V_Cont[1] = DFFEAS(D1L53, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1_V_Cont[2] is VGA_Controller:u1|V_Cont[2]
D1_V_Cont[2] = DFFEAS(D1L56, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1_V_Cont[3] is VGA_Controller:u1|V_Cont[3]
D1_V_Cont[3] = DFFEAS(D1L59, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1L39 is VGA_Controller:u1|LessThan~1088
D1L39 = !D1_V_Cont[1] & !D1_V_Cont[2] & !D1_V_Cont[3];


--D1_V_Cont[4] is VGA_Controller:u1|V_Cont[4]
D1_V_Cont[4] = DFFEAS(D1L62, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1_V_Cont[5] is VGA_Controller:u1|V_Cont[5]
D1_V_Cont[5] = DFFEAS(D1L65, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1L40 is VGA_Controller:u1|LessThan~1089
D1L40 = D1L39 & !D1_V_Cont[4] # !D1_V_Cont[5];


--D1_V_Cont[9] is VGA_Controller:u1|V_Cont[9]
D1_V_Cont[9] = DFFEAS(D1L77, CCD1_MCLK, E1_oRST_2,  , D1L5,  ,  , D1L45,  );


--D1L41 is VGA_Controller:u1|LessThan~1090
D1L41 = D1_V_Cont[4] # D1_V_Cont[5] # !D1L39 # !D1L38;


--D1L99 is VGA_Controller:u1|oVGA_R~216
D1L99 = D1_V_Cont[9] & (!D1L41) # !D1_V_Cont[9] & (!D1L40 # !D1L38);


--D1_H_Cont[4] is VGA_Controller:u1|H_Cont[4]
D1_H_Cont[4] = DFFEAS(D1L20, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  , D1L46,  );


--D1_H_Cont[5] is VGA_Controller:u1|H_Cont[5]
D1_H_Cont[5] = DFFEAS(D1L23, CCD1_MCLK, E1_oRST_2,  ,  ,  ,  , D1L46,  );


--D1_H_Cont[6] is VGA_Controller:u1|H_Cont[6]