de2_ccd_pip.map.rpt

altera de2 开发板 vga lcd控制quatus 工程

+-------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+------------------------------------------------+
; Assignment                      ; Value ; From ; To                                             ;
+---------------------------------+-------+------+------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                              ;
+---------------------------------+-------+------+------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated ;
+---------------------------------+-------+-----------------+----------------------------------------------------------------+
; Assignment                      ; Value ; From            ; To                                                             ;
+---------------------------------+-------+-----------------+----------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -               ; -                                                              ;
; REMOVE_DUPLICATE_REGISTERS      ; OFF   ; -               ; -                                                              ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -               ; -                                                              ;
; SUPPRESS_DA_RULE_INTERNAL       ; d102  ; -               ; -                                                              ;
; SUPPRESS_DA_RULE_INTERNAL       ; s102  ; -               ; -                                                              ;
; POWER_UP_LEVEL                  ; LOW   ; -               ; p0addr                                                         ;
; CUT                             ; ON    ; rdptr_g         ; ws_dgrp|dffpipe10|dffe11a                                      ;
; CUT                             ; ON    ; delayed_wrptr_g ; rs_dgwp|dffpipe7|dffe8a                                        ;
+---------------------------------+-------+-----------------+----------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p ;
+---------------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                          ;
+---------------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                           ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; counter_ffa0                                                                                                ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; parity_ff                                                                                                   ;
+---------------------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_egc:wrptr_gp ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                         ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                          ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                    ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                     ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_mcc:rdaclr ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                           ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                            ;
; SUPPRESS_DA_RULE_INTERNAL       ; c106  ; -    ; -                                                                                            ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_brp ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                           ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                            ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_bwp ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                           ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                            ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp ;
+-----------------------+-------+------+----------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                             ;
+-----------------------+-------+------+----------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                              ;
+-----------------------+-------+------+----------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe7 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_brp ;