de2_ccd_pip.map.rpt

altera de2 开发板 vga lcd控制quatus 工程

104. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp
105. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe7
106. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_brp
107. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_bwp
108. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp
109. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe10
110. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component
111. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
112. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
113. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_egc:wrptr_gp
114. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram
115. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
116. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_mcc:rdaclr
117. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_brp
118. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_bwp
119. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp
120. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe7
121. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_brp
122. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_bwp
123. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp
124. Source assignments for Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe10
125. Source assignments for Mirror_Col_2X:u11|Stack_2X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated
126. Source assignments for Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated
127. Source assignments for Mirror_Col_2X:u11|Stack_2X_RAM:comb_131|altsyncram:altsyncram_component|altsyncram_9cn1:auto_generated
128. Source assignments for Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated
129. Source assignments for Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated
130. Source assignments for Mirror_Col_4X:u12|Stack_4X_RAM:comb_131|altsyncram:altsyncram_component|altsyncram_f9n1:auto_generated
131. Analysis & Elaboration Settings
132. Parameter Settings for User Entity Instance: LCM_PLL:p0|altpll:altpll_component
133. Parameter Settings for User Entity Instance: LCM_Controller:u0
134. Parameter Settings for User Entity Instance: VGA_Controller:u1
135. Parameter Settings for User Entity Instance: RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
136. Parameter Settings for User Entity Instance: RAW2RGB_4X:v4|Line_Buffer:u0|altshift_taps:altshift_taps_component
137. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6
138. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component
139. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|control_interface:control1
140. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|command:command1
141. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|sdr_data_path:data_path1
142. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component
143. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component
144. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo3|dcfifo:dcfifo_component
145. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_WR_FIFO:write_fifo4|dcfifo:dcfifo_component
146. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component
147. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component
148. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo3|dcfifo:dcfifo_component
149. Parameter Settings for User Entity Instance: Sdram_Control_8Port:u6|Sdram_RD_FIFO:read_fifo4|dcfifo:dcfifo_component
150. Parameter Settings for User Entity Instance: I2C_CCD_Config:u7
151. Parameter Settings for User Entity Instance: I2C_CCD_Config:u8
152. Parameter Settings for User Entity Instance: I2S_LCM_Config:u9
153. Parameter Settings for User Entity Instance: I2S_LCM_Config:u9|I2S_Controller:u0
154. Parameter Settings for User Entity Instance: I2C_AV_Config:u10
155. Parameter Settings for User Entity Instance: Mirror_Col_2X:u11|Stack_2X_RAM:comb_63|altsyncram:altsyncram_component
156. Parameter Settings for User Entity Instance: Mirror_Col_2X:u11|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component
157. Parameter Settings for User Entity Instance: Mirror_Col_2X:u11|Stack_2X_RAM:comb_131|altsyncram:altsyncram_component
158. Parameter Settings for User Entity Instance: Mirror_Col_4X:u12|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component
159. Parameter Settings for User Entity Instance: Mirror_Col_4X:u12|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component
160. Parameter Settings for User Entity Instance: Mirror_Col_4X:u12|Stack_4X_RAM:comb_131|altsyncram:altsyncram_component
161. altshift_taps Parameter Settings by Entity Instance
162. dcfifo Parameter Settings by Entity Instance
163. Analysis & Elaboration Messages



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+--------------------------------------------------------------------------+
; Analysis & Elaboration Summary                                           ;
+-------------------------------+------------------------------------------+
; Analysis & Elaboration Status ; Successful - Mon Sep 01 15:15:34 2008    ;
; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                 ; DE2_CCD_PIP                              ;
; Top-level Entity Name         ; DE2_CCD_PIP                              ;
; Family                        ; Cyclone II                               ;
+-------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated|altsyncram_4m81:altsyncram2 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                    ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                     ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for RAW2RGB_4X:v4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated|altsyncram_4m81:altsyncram2 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                    ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                     ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------+