📄 de2_ccd_pip.v
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reg CCD2_MCLK; // CCD Master Clock
wire [15:0] Read_DATA1;
wire [15:0] Read_DATA2;
wire [15:0] Read_DATA3;
wire [15:0] Read_DATA4;
wire VGA_CTRL_CLK;
wire [9:0] mCCD1_DATA;
wire mCCD1_DVAL;
wire mCCD1_DVAL_d;
wire [9:0] mCCD2_DATA;
wire mCCD2_DVAL;
wire mCCD2_DVAL_d;
wire [10:0] X1_Cont;
wire [10:0] Y1_Cont;
wire [31:0] Frame1_Cont;
wire [9:0] mCCD1_R;
wire [9:0] mCCD1_G;
wire [9:0] mCCD1_B;
wire [10:0] X2_Cont;
wire [10:0] Y2_Cont;
wire [31:0] Frame2_Cont;
wire [9:0] mCCD2_R;
wire [9:0] mCCD2_G;
wire [9:0] mCCD2_B;
wire DLY_RST_0;
wire DLY_RST_1;
wire DLY_RST_2;
wire Read1;
wire Read2;
wire Pre_Read;
wire [9:0] X_ADDR;
wire [9:0] Y_ADDR;
reg [9:0] rCCD1_DATA;
reg rCCD1_LVAL;
reg rCCD1_FVAL;
reg [9:0] rCCD2_DATA;
reg rCCD2_LVAL;
reg rCCD2_FVAL;
wire [9:0] sCCD1_R;
wire [9:0] sCCD1_G;
wire [9:0] sCCD1_B;
wire sCCD1_DVAL;
wire [9:0] sCCD2_R;
wire [9:0] sCCD2_G;
wire [9:0] sCCD2_B;
wire sCCD2_DVAL;
// For Sensor 1
assign CCD1_DATA[0] = GPIO_1[0];
assign CCD1_DATA[1] = GPIO_1[1];
assign CCD1_DATA[2] = GPIO_1[5];
assign CCD1_DATA[3] = GPIO_1[3];
assign CCD1_DATA[4] = GPIO_1[2];
assign CCD1_DATA[5] = GPIO_1[4];
assign CCD1_DATA[6] = GPIO_1[6];
assign CCD1_DATA[7] = GPIO_1[7];
assign CCD1_DATA[8] = GPIO_1[8];
assign CCD1_DATA[9] = GPIO_1[9];
assign GPIO_1[11] = CCD1_MCLK;
//assign GPIO_1[15] = CCD1_SDAT;
//assign GPIO_1[14] = CCD1_SCLK;
assign CCD1_FVAL = GPIO_1[13];
assign CCD1_LVAL = GPIO_1[12];
assign CCD1_PIXCLK = GPIO_1[10];
// For Sensor 2
assign CCD2_DATA[0] = GPIO_1[0+20];
assign CCD2_DATA[1] = GPIO_1[1+20];
assign CCD2_DATA[2] = GPIO_1[5+20];
assign CCD2_DATA[3] = GPIO_1[3+20];
assign CCD2_DATA[4] = GPIO_1[2+20];
assign CCD2_DATA[5] = GPIO_1[4+20];
assign CCD2_DATA[6] = GPIO_1[6+20];
assign CCD2_DATA[7] = GPIO_1[7+20];
assign CCD2_DATA[8] = GPIO_1[8+20];
assign CCD2_DATA[9] = GPIO_1[9+20];
assign GPIO_1[11+20] = CCD2_MCLK;
//assign GPIO_1[15+20] = CCD2_SDAT;
//assign GPIO_1[14+20] = CCD2_SCLK;
assign CCD2_FVAL = GPIO_1[13+20];
assign CCD2_LVAL = GPIO_1[12+20];
assign CCD2_PIXCLK = GPIO_1[10+20];
assign LEDR = SW;
//test
wire [3:0] Full;
wire [3:0] Empty;
assign LEDG = Y1_Cont;
//assign LEDG = {Full,Empty};
assign VGA_CTRL_CLK= CCD1_MCLK;
assign VGA_CLK = ~CCD1_MCLK;
always@(posedge CLOCK_50) CCD1_MCLK <= ~CCD1_MCLK;
always@(posedge CLOCK_50) CCD2_MCLK <= ~CCD2_MCLK;
always@(posedge CCD1_PIXCLK)
begin
rCCD1_DATA <= CCD1_DATA;
rCCD1_LVAL <= CCD1_LVAL;
rCCD1_FVAL <= CCD1_FVAL;
end
always@(posedge CCD2_PIXCLK)
begin
rCCD2_DATA <= CCD2_DATA;
rCCD2_LVAL <= CCD2_LVAL;
rCCD2_FVAL <= CCD2_FVAL;
end
LCM_PLL p0 ( .inclk0(CLOCK_27),.c0(CLK_18));
LCM_Controller u0 ( // Host Side
.iRed( Read_DATA4[9:2] ),
.iGreen( {Read_DATA4[14:10],Read_DATA3[14:12]} ),
.iBlue( Read_DATA3[9:2] ),
// LCM Side
.LCM_DATA(LCM_DATA),
.LCM_VSYNC(LCM_VSYNC),
.LCM_HSYNC(LCM_HSYNC),
.LCM_DCLK(LCM_DCLK),
.LCM_SHDB(LCM_SHDB),
.LCM_GRST(LCM_GRST),
// Control Signals
.oDATA_REQ(Read2),
.iCLK(CLK_18),
.iRST_N(DLY_RST_2) );
VGA_Controller u1 ( // Host Side
.oRequest(Read1),
.iRed( Read_DATA2[9:0] ),
.iGreen( {Read_DATA2[14:10],Read_DATA1[14:10]} ),
.iBlue( Read_DATA1[9:0] ),
.oCoord_X(X_ADDR),
.oCoord_Y(Y_ADDR),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST_2) );
Reset_Delay u2 ( .iCLK(CLOCK_50),
.iRST(KEY[0]),
.oRST_0(DLY_RST_0),
.oRST_1(DLY_RST_1),
.oRST_2(DLY_RST_2) );
CCD_Capture u3 ( .oDATA(mCCD1_DATA),
.oDVAL(mCCD1_DVAL),
.oX_Cont(X1_Cont),
.oY_Cont(Y1_Cont),
.oFrame_Cont(Frame1_Cont),
.iDATA(rCCD1_DATA),
.iFVAL(rCCD1_FVAL),
.iLVAL(rCCD1_LVAL),
.iSTART(!KEY[3]),
.iEND(!KEY[2]),
.iCLK(CCD1_PIXCLK),
.iRST(DLY_RST_1) );
CCD_Capture v3 ( .oDATA(mCCD2_DATA),
.oDVAL(mCCD2_DVAL),
.oX_Cont(X2_Cont),
.oY_Cont(Y2_Cont),
.oFrame_Cont(Frame2_Cont),
.iDATA(rCCD2_DATA),
.iFVAL(rCCD2_FVAL),
.iLVAL(rCCD2_LVAL),
.iSTART(!KEY[3]),
.iEND(!KEY[2]),
.iCLK(CCD2_PIXCLK),
.iRST(DLY_RST_1) );
RAW2RGB_2X u4 ( .oRed(mCCD1_R),
.oGreen(mCCD1_G),
.oBlue(mCCD1_B),
.oDVAL(mCCD1_DVAL_d),
.iX_Cont(X1_Cont),
.iY_Cont(Y1_Cont),
.iDATA(mCCD1_DATA),
.iDVAL(mCCD1_DVAL),
.iCLK(CCD1_PIXCLK),
.iRST(DLY_RST_1) );
RAW2RGB_4X v4 ( .oRed(mCCD2_R),
.oGreen(mCCD2_G),
.oBlue(mCCD2_B),
.oDVAL(mCCD2_DVAL_d),
.iX_Cont(X2_Cont),
.iY_Cont(Y2_Cont),
.iDATA(mCCD2_DATA),
.iDVAL(mCCD2_DVAL),
.iCLK(CCD2_PIXCLK),
.iRST(DLY_RST_1) );
SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1),
.oSEG2(HEX2),.oSEG3(HEX3),
.oSEG4(HEX4),.oSEG5(HEX5),
.oSEG6(HEX6),.oSEG7(HEX7),
.iDIG(Frame1_Cont) );
Sdram_Control_8Port u6 ( // HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA( {1'b0,
sCCD1_G[4:0],
sCCD1_B[9:0]}),
.WR1(sCCD1_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*512),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD1_PIXCLK),
.WR1_FULL(Full[0]),
// FIFO Write Side 2
.WR2_DATA( {1'b0,
sCCD1_G[9:5],
sCCD1_R[9:0]}),
.WR2(sCCD1_DVAL),
.WR2_ADDR(22'h100000),
.WR2_MAX_ADDR(22'h100000+640*512),
.WR2_LENGTH(9'h100),
.WR2_LOAD(!DLY_RST_0),
.WR2_CLK(CCD1_PIXCLK),
.WR2_FULL(Full[1]),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read1),
.RD1_ADDR(640*16),
.RD1_MAX_ADDR(640*496),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
.RD1_EMPTY(Empty[0]),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(Read1),
.RD2_ADDR(22'h100000+640*16),
.RD2_MAX_ADDR(22'h100000+640*496),
.RD2_LENGTH(9'h100),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(VGA_CTRL_CLK),
.RD2_EMPTY(Empty[1]),
// FIFO Write Side 3
.WR3_DATA( {1'b0,
sCCD2_G[4:0],
sCCD2_B[9:0]}),
.WR3(sCCD2_DVAL),
.WR3_ADDR(22'h200000),
.WR3_MAX_ADDR(22'h200000+320*256),
.WR3_LENGTH(9'h100),
.WR3_LOAD(!DLY_RST_0),
.WR3_CLK(CCD2_PIXCLK),
.WR3_FULL(Full[2]),
// FIFO Write Side 4
.WR4_DATA( {1'b0,
sCCD2_G[9:5],
sCCD2_R[9:0]}),
.WR4(sCCD2_DVAL),
.WR4_ADDR(22'h280000),
.WR4_MAX_ADDR(22'h280000+320*256),
.WR4_LENGTH(9'h100),
.WR4_LOAD(!DLY_RST_0),
.WR4_CLK(CCD2_PIXCLK),
.WR4_FULL(Full[3]),
// FIFO Read Side 3
.RD3_DATA(Read_DATA3),
.RD3(Read2),
.RD3_ADDR(22'h200000+320*8),
.RD3_MAX_ADDR(22'h200000+320*248),
.RD3_LENGTH(9'h100),
.RD3_LOAD(!DLY_RST_0),
.RD3_CLK(CLK_18),
.RD3_EMPTY(Empty[2]),
// FIFO Read Side 4
.RD4_DATA(Read_DATA4),
.RD4(Read2),
.RD4_ADDR(22'h280000+320*8),
.RD4_MAX_ADDR(22'h280000+320*248),
.RD4_LENGTH(9'h100),
.RD4_LOAD(!DLY_RST_0),
.RD4_CLK(CLK_18),
.RD4_EMPTY(Empty[3]),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
I2C_CCD_Config u7 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[1]),
.iExposure(SW[15:0]),
// I2C Side
.I2C_SCLK(GPIO_1[14]),
.I2C_SDAT(GPIO_1[15]) );
I2C_CCD_Config u8 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[1]),
.iExposure(SW[15:0]),
// I2C Side
.I2C_SCLK(GPIO_1[34]),
.I2C_SDAT(GPIO_1[35]) );
I2S_LCM_Config u9 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[0]),
// I2C Side
.I2S_SCLK(LCM_SCLK),
.I2S_SDAT(GPIO_0[34]),
.I2S_SCEN(LCM_SCEN) );
I2C_AV_Config u10 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[0]),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
Mirror_Col_2X u11 ( // Input Side
.iCCD_R(mCCD1_R),
.iCCD_G(mCCD1_G),
.iCCD_B(mCCD1_B),
.iCCD_DVAL(mCCD1_DVAL_d),
.iCCD_PIXCLK(CCD1_PIXCLK),
.iRST_N(DLY_RST_1),
// Output Side
.oCCD_R(sCCD1_R),
.oCCD_G(sCCD1_G),
.oCCD_B(sCCD1_B),
.oCCD_DVAL(sCCD1_DVAL));
Mirror_Col_4X u12 ( // Input Side
.iCCD_R(mCCD2_R),
.iCCD_G(mCCD2_G),
.iCCD_B(mCCD2_B),
.iCCD_DVAL(mCCD2_DVAL_d),
.iCCD_PIXCLK(CCD2_PIXCLK),
.iRST_N(DLY_RST_1),
// Output Side
.oCCD_R(sCCD2_R),
.oCCD_G(sCCD2_G),
.oCCD_B(sCCD2_B),
.oCCD_DVAL(sCCD2_DVAL));
endmodule
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