de2_ccd_pip.fit.eqn

altera de2 开发板 vga lcd控制quatus 工程

PB3_q_a[3] = PB3_q_a[0]_PORT_A_data_out_reg[2];

--PB3_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2] at M4K_X26_Y17
PB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[0]_PORT_A_data_in_reg = DFFE(PB3_q_a[0]_PORT_A_data_in, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_data_in = BUS(J1_mDATAOUT[0], J1_mDATAOUT[2], J1_mDATAOUT[3], J1_mDATAOUT[5], J1_mDATAOUT[6], J1_mDATAOUT[11]);
PB3_q_a[0]_PORT_B_data_in_reg = DFFE(PB3_q_a[0]_PORT_B_data_in, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[0]_PORT_A_address_reg = DFFE(PB3_q_a[0]_PORT_A_address, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[0]_PORT_B_address_reg = DFFE(PB3_q_a[0]_PORT_B_address, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_write_enable = GND;
PB3_q_a[0]_PORT_A_write_enable_reg = DFFE(PB3_q_a[0]_PORT_A_write_enable, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[0]_PORT_B_write_enable_reg = DFFE(PB3_q_a[0]_PORT_B_write_enable, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_clock_0 = GLOBAL(A1L9);
PB3_q_a[0]_clock_1 = GLOBAL(R2L2);
PB3_q_a[0]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[0]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[0]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[0]_PORT_A_data_out = MEMORY(PB3_q_a[0]_PORT_A_data_in_reg, PB3_q_a[0]_PORT_B_data_in_reg, PB3_q_a[0]_PORT_A_address_reg, PB3_q_a[0]_PORT_B_address_reg, PB3_q_a[0]_PORT_A_write_enable_reg, PB3_q_a[0]_PORT_B_write_enable_reg, , , PB3_q_a[0]_clock_0, PB3_q_a[0]_clock_1, PB3_q_a[0]_clock_enable_0, PB3_q_a[0]_clock_enable_1, , PB3_q_a[0]_clear_1);
PB3_q_a[0]_PORT_A_data_out_reg = DFFE(PB3_q_a[0]_PORT_A_data_out, PB3_q_a[0]_clock_0, PB3_q_a[0]_clear_1, , PB3_q_a[0]_clock_enable_0);
PB3_q_a[2] = PB3_q_a[0]_PORT_A_data_out_reg[1];


--D1L83 is VGA_Controller:u1|oVGA_B[0]~60 at LCCOMB_X25_Y32_N26
D1L83 = PB3_q_a[0] & D1L99 & D1L100;


--PB3_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X26_Y18
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = GLOBAL(A1L9);
PB3_q_a[1]_clock_1 = GLOBAL(R2L2);
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1] = PB3_q_a[1]_PORT_A_data_out_reg[0];

--PB3_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14] at M4K_X26_Y18
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = GLOBAL(A1L9);
PB3_q_a[1]_clock_1 = GLOBAL(R2L2);
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[14] = PB3_q_a[1]_PORT_A_data_out_reg[8];

--PB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X26_Y18
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = GLOBAL(A1L9);
PB3_q_a[1]_clock_1 = GLOBAL(R2L2);
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[13] = PB3_q_a[1]_PORT_A_data_out_reg[7];

--PB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X26_Y18
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = GLOBAL(A1L9);
PB3_q_a[1]_clock_1 = GLOBAL(R2L2);
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[12] = PB3_q_a[1]_PORT_A_data_out_reg[6];

--PB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X26_Y18
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = GLOBAL(A1L9);
PB3_q_a[1]_clock_1 = GLOBAL(R2L2);
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[10] = PB3_q_a[1]_PORT_A_data_out_reg[5];

--PB3_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X26_Y18
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = GLOBAL(A1L9);
PB3_q_a[1]_clock_1 = GLOBAL(R2L2);
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[9] = PB3_q_a[1]_PORT_A_data_out_reg[4];

--PB3_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X26_Y18
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(PB3_q_a[1]_PORT_B_data_in, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[1]_PORT_A_address_reg = DFFE(PB3_q_a[1]_PORT_A_address, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[1]_PORT_B_address_reg = DFFE(PB3_q_a[1]_PORT_B_address, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_PORT_A_write_enable = GND;
PB3_q_a[1]_PORT_A_write_enable_reg = DFFE(PB3_q_a[1]_PORT_A_write_enable, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[1]_PORT_B_write_enable_reg = DFFE(PB3_q_a[1]_PORT_B_write_enable, PB3_q_a[1]_clock_1, , , PB3_q_a[1]_clock_enable_1);
PB3_q_a[1]_clock_0 = GLOBAL(A1L9);
PB3_q_a[1]_clock_1 = GLOBAL(R2L2);
PB3_q_a[1]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[1]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[1]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[1]_PORT_A_data_out = MEMORY(PB3_q_a[1]_PORT_A_data_in_reg, PB3_q_a[1]_PORT_B_data_in_reg, PB3_q_a[1]_PORT_A_address_reg, PB3_q_a[1]_PORT_B_address_reg, PB3_q_a[1]_PORT_A_write_enable_reg, PB3_q_a[1]_PORT_B_write_enable_reg, , , PB3_q_a[1]_clock_0, PB3_q_a[1]_clock_1, PB3_q_a[1]_clock_enable_0, PB3_q_a[1]_clock_enable_1, , PB3_q_a[1]_clear_1);
PB3_q_a[1]_PORT_A_data_out_reg = DFFE(PB3_q_a[1]_PORT_A_data_out, PB3_q_a[1]_clock_0, PB3_q_a[1]_clear_1, , PB3_q_a[1]_clock_enable_0);
PB3_q_a[8] = PB3_q_a[1]_PORT_A_data_out_reg[3];

--PB3_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7] at M4K_X26_Y18
PB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[1]_PORT_A_data_in_reg = DFFE(PB3_q_a[1]_PORT_A_data_in, PB3_q_a[1]_clock_0, , , PB3_q_a[1]_clock_enable_0);
PB3_q_a[1]_PORT_B_data_in = BUS(J1_mDATAOUT[1], J1_mDATAOUT[4], J1_mDATAOUT[7], J1_mDATAOUT[8], J1_mDATAOUT[9], J1_mDATAOUT[10], J1_mDATAOUT[12], J1_mDATAOUT[13], J1_mDATAOUT[14]);
PB3_q_a[1]_PORT_B_data_in_reg = DFFE(