de2_ccd_pip.fit.eqn

altera de2 开发板 vga lcd控制quatus 工程

--D1_V_Cont[9] is VGA_Controller:u1|V_Cont[9] at LCFF_X17_Y30_N27
D1_V_Cont[9] = DFFEAS(D1L77, GLOBAL(A1L9), GLOBAL(E1L84),  , D1L5,  ,  , D1L45,  );


--D1L41 is VGA_Controller:u1|LessThan~1090 at LCCOMB_X17_Y31_N6
D1L41 = D1_V_Cont[4] # D1_V_Cont[5] # !D1L38 # !D1L39;


--D1L99 is VGA_Controller:u1|oVGA_R~216 at LCCOMB_X17_Y31_N22
D1L99 = D1_V_Cont[9] & !D1L41 # !D1_V_Cont[9] & (!D1L40 # !D1L38);


--D1_H_Cont[4] is VGA_Controller:u1|H_Cont[4] at LCFF_X18_Y31_N15
D1_H_Cont[4] = DFFEAS(D1L20, GLOBAL(A1L9), GLOBAL(E1L84),  ,  ,  ,  , D1L46,  );


--D1_H_Cont[5] is VGA_Controller:u1|H_Cont[5] at LCFF_X18_Y31_N17
D1_H_Cont[5] = DFFEAS(D1L23, GLOBAL(A1L9), GLOBAL(E1L84),  ,  ,  ,  , D1L46,  );


--D1_H_Cont[6] is VGA_Controller:u1|H_Cont[6] at LCFF_X18_Y31_N19
D1_H_Cont[6] = DFFEAS(D1L27, GLOBAL(A1L9), GLOBAL(E1L84),  ,  ,  ,  , D1L46,  );


--D1L1 is VGA_Controller:u1|Equal~115 at LCCOMB_X18_Y31_N2
D1L1 = !D1_H_Cont[5] & !D1_H_Cont[4] & !D1_H_Cont[6];


--D1_H_Cont[7] is VGA_Controller:u1|H_Cont[7] at LCFF_X18_Y31_N21
D1_H_Cont[7] = DFFEAS(D1L30, GLOBAL(A1L9), GLOBAL(E1L84),  ,  ,  ,  , D1L46,  );


--D1_H_Cont[8] is VGA_Controller:u1|H_Cont[8] at LCFF_X18_Y31_N23
D1_H_Cont[8] = DFFEAS(D1L33, GLOBAL(A1L9), GLOBAL(E1L84),  ,  ,  ,  , D1L46,  );


--D1_H_Cont[9] is VGA_Controller:u1|H_Cont[9] at LCFF_X18_Y31_N25
D1_H_Cont[9] = DFFEAS(D1L36, GLOBAL(A1L9), GLOBAL(E1L84),  ,  ,  ,  , D1L46,  );


--D1L100 is VGA_Controller:u1|oVGA_R~217 at LCCOMB_X17_Y31_N0
D1L100 = D1_H_Cont[8] & (D1L1 & !D1_H_Cont[7] # !D1_H_Cont[9]) # !D1_H_Cont[8] & (D1_H_Cont[9] # !D1L1 & D1_H_Cont[7]);


--D1L94 is VGA_Controller:u1|oVGA_R[0]~218 at LCCOMB_X25_Y32_N16
D1L94 = PB3_q_a[10] & D1L99 & D1L100;


--D1L95 is VGA_Controller:u1|oVGA_R[1]~219 at LCCOMB_X25_Y32_N8
D1L95 = D1L99 & PB3_q_a[11] & D1L100;


--D1L96 is VGA_Controller:u1|oVGA_R[2]~220 at LCCOMB_X25_Y32_N14
D1L96 = D1L99 & PB3_q_a[12] & D1L100;


--D1L97 is VGA_Controller:u1|oVGA_R[3]~221 at LCCOMB_X25_Y32_N12
D1L97 = D1L99 & PB3_q_a[13] & D1L100;


--D1L98 is VGA_Controller:u1|oVGA_R[4]~222 at LCCOMB_X25_Y32_N10
D1L98 = D1L99 & PB3_q_a[14] & D1L100;


--D1L88 is VGA_Controller:u1|oVGA_G[0]~60 at LCCOMB_X25_Y32_N28
D1L88 = D1L99 & PB3_q_a[5] & D1L100;


--D1L89 is VGA_Controller:u1|oVGA_G[1]~61 at LCCOMB_X25_Y32_N20
D1L89 = D1L99 & PB3_q_a[6] & D1L100;


--D1L90 is VGA_Controller:u1|oVGA_G[2]~62 at LCCOMB_X25_Y32_N6
D1L90 = D1L99 & PB3_q_a[7] & D1L100;


--D1L91 is VGA_Controller:u1|oVGA_G[3]~63 at LCCOMB_X25_Y32_N24
D1L91 = D1L99 & PB3_q_a[8] & D1L100;


--D1L92 is VGA_Controller:u1|oVGA_G[4]~64 at LCCOMB_X25_Y32_N4
D1L92 = PB3_q_a[9] & D1L99 & D1L100;


--PB3_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X26_Y17
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 6, Port B Depth: 512, Port B Width: 6
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
PB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[0]_PORT_A_data_in_reg = DFFE(PB3_q_a[0]_PORT_A_data_in, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_data_in = BUS(J1_mDATAOUT[0], J1_mDATAOUT[2], J1_mDATAOUT[3], J1_mDATAOUT[5], J1_mDATAOUT[6], J1_mDATAOUT[11]);
PB3_q_a[0]_PORT_B_data_in_reg = DFFE(PB3_q_a[0]_PORT_B_data_in, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[0]_PORT_A_address_reg = DFFE(PB3_q_a[0]_PORT_A_address, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[0]_PORT_B_address_reg = DFFE(PB3_q_a[0]_PORT_B_address, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_write_enable = GND;
PB3_q_a[0]_PORT_A_write_enable_reg = DFFE(PB3_q_a[0]_PORT_A_write_enable, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[0]_PORT_B_write_enable_reg = DFFE(PB3_q_a[0]_PORT_B_write_enable, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_clock_0 = GLOBAL(A1L9);
PB3_q_a[0]_clock_1 = GLOBAL(R2L2);
PB3_q_a[0]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[0]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[0]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[0]_PORT_A_data_out = MEMORY(PB3_q_a[0]_PORT_A_data_in_reg, PB3_q_a[0]_PORT_B_data_in_reg, PB3_q_a[0]_PORT_A_address_reg, PB3_q_a[0]_PORT_B_address_reg, PB3_q_a[0]_PORT_A_write_enable_reg, PB3_q_a[0]_PORT_B_write_enable_reg, , , PB3_q_a[0]_clock_0, PB3_q_a[0]_clock_1, PB3_q_a[0]_clock_enable_0, PB3_q_a[0]_clock_enable_1, , PB3_q_a[0]_clear_1);
PB3_q_a[0]_PORT_A_data_out_reg = DFFE(PB3_q_a[0]_PORT_A_data_out, PB3_q_a[0]_clock_0, PB3_q_a[0]_clear_1, , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0] = PB3_q_a[0]_PORT_A_data_out_reg[0];

--PB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X26_Y17
PB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[0]_PORT_A_data_in_reg = DFFE(PB3_q_a[0]_PORT_A_data_in, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_data_in = BUS(J1_mDATAOUT[0], J1_mDATAOUT[2], J1_mDATAOUT[3], J1_mDATAOUT[5], J1_mDATAOUT[6], J1_mDATAOUT[11]);
PB3_q_a[0]_PORT_B_data_in_reg = DFFE(PB3_q_a[0]_PORT_B_data_in, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[0]_PORT_A_address_reg = DFFE(PB3_q_a[0]_PORT_A_address, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[0]_PORT_B_address_reg = DFFE(PB3_q_a[0]_PORT_B_address, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_write_enable = GND;
PB3_q_a[0]_PORT_A_write_enable_reg = DFFE(PB3_q_a[0]_PORT_A_write_enable, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[0]_PORT_B_write_enable_reg = DFFE(PB3_q_a[0]_PORT_B_write_enable, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_clock_0 = GLOBAL(A1L9);
PB3_q_a[0]_clock_1 = GLOBAL(R2L2);
PB3_q_a[0]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[0]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[0]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[0]_PORT_A_data_out = MEMORY(PB3_q_a[0]_PORT_A_data_in_reg, PB3_q_a[0]_PORT_B_data_in_reg, PB3_q_a[0]_PORT_A_address_reg, PB3_q_a[0]_PORT_B_address_reg, PB3_q_a[0]_PORT_A_write_enable_reg, PB3_q_a[0]_PORT_B_write_enable_reg, , , PB3_q_a[0]_clock_0, PB3_q_a[0]_clock_1, PB3_q_a[0]_clock_enable_0, PB3_q_a[0]_clock_enable_1, , PB3_q_a[0]_clear_1);
PB3_q_a[0]_PORT_A_data_out_reg = DFFE(PB3_q_a[0]_PORT_A_data_out, PB3_q_a[0]_clock_0, PB3_q_a[0]_clear_1, , PB3_q_a[0]_clock_enable_0);
PB3_q_a[11] = PB3_q_a[0]_PORT_A_data_out_reg[5];

--PB3_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6] at M4K_X26_Y17
PB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[0]_PORT_A_data_in_reg = DFFE(PB3_q_a[0]_PORT_A_data_in, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_data_in = BUS(J1_mDATAOUT[0], J1_mDATAOUT[2], J1_mDATAOUT[3], J1_mDATAOUT[5], J1_mDATAOUT[6], J1_mDATAOUT[11]);
PB3_q_a[0]_PORT_B_data_in_reg = DFFE(PB3_q_a[0]_PORT_B_data_in, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[0]_PORT_A_address_reg = DFFE(PB3_q_a[0]_PORT_A_address, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[0]_PORT_B_address_reg = DFFE(PB3_q_a[0]_PORT_B_address, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_write_enable = GND;
PB3_q_a[0]_PORT_A_write_enable_reg = DFFE(PB3_q_a[0]_PORT_A_write_enable, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[0]_PORT_B_write_enable_reg = DFFE(PB3_q_a[0]_PORT_B_write_enable, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_clock_0 = GLOBAL(A1L9);
PB3_q_a[0]_clock_1 = GLOBAL(R2L2);
PB3_q_a[0]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[0]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[0]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[0]_PORT_A_data_out = MEMORY(PB3_q_a[0]_PORT_A_data_in_reg, PB3_q_a[0]_PORT_B_data_in_reg, PB3_q_a[0]_PORT_A_address_reg, PB3_q_a[0]_PORT_B_address_reg, PB3_q_a[0]_PORT_A_write_enable_reg, PB3_q_a[0]_PORT_B_write_enable_reg, , , PB3_q_a[0]_clock_0, PB3_q_a[0]_clock_1, PB3_q_a[0]_clock_enable_0, PB3_q_a[0]_clock_enable_1, , PB3_q_a[0]_clear_1);
PB3_q_a[0]_PORT_A_data_out_reg = DFFE(PB3_q_a[0]_PORT_A_data_out, PB3_q_a[0]_clock_0, PB3_q_a[0]_clear_1, , PB3_q_a[0]_clock_enable_0);
PB3_q_a[6] = PB3_q_a[0]_PORT_A_data_out_reg[4];

--PB3_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5] at M4K_X26_Y17
PB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[0]_PORT_A_data_in_reg = DFFE(PB3_q_a[0]_PORT_A_data_in, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_data_in = BUS(J1_mDATAOUT[0], J1_mDATAOUT[2], J1_mDATAOUT[3], J1_mDATAOUT[5], J1_mDATAOUT[6], J1_mDATAOUT[11]);
PB3_q_a[0]_PORT_B_data_in_reg = DFFE(PB3_q_a[0]_PORT_B_data_in, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[0]_PORT_A_address_reg = DFFE(PB3_q_a[0]_PORT_A_address, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[0]_PORT_B_address_reg = DFFE(PB3_q_a[0]_PORT_B_address, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_write_enable = GND;
PB3_q_a[0]_PORT_A_write_enable_reg = DFFE(PB3_q_a[0]_PORT_A_write_enable, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[0]_PORT_B_write_enable_reg = DFFE(PB3_q_a[0]_PORT_B_write_enable, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_clock_0 = GLOBAL(A1L9);
PB3_q_a[0]_clock_1 = GLOBAL(R2L2);
PB3_q_a[0]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[0]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[0]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[0]_PORT_A_data_out = MEMORY(PB3_q_a[0]_PORT_A_data_in_reg, PB3_q_a[0]_PORT_B_data_in_reg, PB3_q_a[0]_PORT_A_address_reg, PB3_q_a[0]_PORT_B_address_reg, PB3_q_a[0]_PORT_A_write_enable_reg, PB3_q_a[0]_PORT_B_write_enable_reg, , , PB3_q_a[0]_clock_0, PB3_q_a[0]_clock_1, PB3_q_a[0]_clock_enable_0, PB3_q_a[0]_clock_enable_1, , PB3_q_a[0]_clear_1);
PB3_q_a[0]_PORT_A_data_out_reg = DFFE(PB3_q_a[0]_PORT_A_data_out, PB3_q_a[0]_clock_0, PB3_q_a[0]_clear_1, , PB3_q_a[0]_clock_enable_0);
PB3_q_a[5] = PB3_q_a[0]_PORT_A_data_out_reg[3];

--PB3_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3] at M4K_X26_Y17
PB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
PB3_q_a[0]_PORT_A_data_in_reg = DFFE(PB3_q_a[0]_PORT_A_data_in, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_data_in = BUS(J1_mDATAOUT[0], J1_mDATAOUT[2], J1_mDATAOUT[3], J1_mDATAOUT[5], J1_mDATAOUT[6], J1_mDATAOUT[11]);
PB3_q_a[0]_PORT_B_data_in_reg = DFFE(PB3_q_a[0]_PORT_B_data_in, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_address = BUS(GB3_power_modified_counter_values[0], GB3_power_modified_counter_values[1], GB3_power_modified_counter_values[2], GB3_power_modified_counter_values[3], GB3_power_modified_counter_values[4], GB3_power_modified_counter_values[5], GB3_power_modified_counter_values[6], GB3_power_modified_counter_values[7], GB3_power_modified_counter_values[8]);
PB3_q_a[0]_PORT_A_address_reg = DFFE(PB3_q_a[0]_PORT_A_address, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_address = BUS(EB3_wrptr_g[0], EB3_wrptr_g[1], EB3_wrptr_g[2], EB3_wrptr_g[3], EB3_wrptr_g[4], EB3_wrptr_g[5], EB3_wrptr_g[6], EB3_wrptr_g[7], EB3_wrptr_g[8]);
PB3_q_a[0]_PORT_B_address_reg = DFFE(PB3_q_a[0]_PORT_B_address, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_PORT_A_write_enable = GND;
PB3_q_a[0]_PORT_A_write_enable_reg = DFFE(PB3_q_a[0]_PORT_A_write_enable, PB3_q_a[0]_clock_0, , , PB3_q_a[0]_clock_enable_0);
PB3_q_a[0]_PORT_B_write_enable = EB3_valid_wrreq;
PB3_q_a[0]_PORT_B_write_enable_reg = DFFE(PB3_q_a[0]_PORT_B_write_enable, PB3_q_a[0]_clock_1, , , PB3_q_a[0]_clock_enable_1);
PB3_q_a[0]_clock_0 = GLOBAL(A1L9);
PB3_q_a[0]_clock_1 = GLOBAL(R2L2);
PB3_q_a[0]_clock_enable_0 = EB3_valid_rdreq;
PB3_q_a[0]_clock_enable_1 = EB3_valid_wrreq;
PB3_q_a[0]_clear_1 = !GLOBAL(E1L78);
PB3_q_a[0]_PORT_A_data_out = MEMORY(PB3_q_a[0]_PORT_A_data_in_reg, PB3_q_a[0]_PORT_B_data_in_reg, PB3_q_a[0]_PORT_A_address_reg, PB3_q_a[0]_PORT_B_address_reg, PB3_q_a[0]_PORT_A_write_enable_reg, PB3_q_a[0]_PORT_B_write_enable_reg, , , PB3_q_a[0]_clock_0, PB3_q_a[0]_clock_1, PB3_q_a[0]_clock_enable_0, PB3_q_a[0]_clock_enable_1, , PB3_q_a[0]_clear_1);
PB3_q_a[0]_PORT_A_data_out_reg = DFFE(PB3_q_a[0]_PORT_A_data_out, PB3_q_a[0]_clock_0, PB3_q_a[0]_clear_1, , PB3_q_a[0]_clock_enable_0);