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📄 fifoctlr_cc_tb.vhd

📁 这是一个基于xilinx ISE9.1的一个历程
💻 VHD
📖 第 1 页 / 共 2 页
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12 
		-- --------------------		WAIT FOR 12 ns; -- Time=720 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001101"); --D		-- --------------------		WAIT FOR 8 ns; -- Time=728 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=740 ns		-- --------------------		WAIT FOR 8 ns; -- Time=748 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=760 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001110"); --E		-- --------------------		WAIT FOR 8 ns; -- Time=768 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=780 ns		-- --------------------		WAIT FOR 8 ns; -- Time=788 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=800 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001111"); --F		-- --------------------		WAIT FOR 8 ns; -- Time=808 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=820 ns		-- --------------------		WAIT FOR 8 ns; -- Time=828 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=840 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000010000"); --10		-- --------------------		WAIT FOR 8 ns; -- Time=848 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=860 ns		-- --------------------		WAIT FOR 8 ns; -- Time=868 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=880 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000010001"); --11		-- --------------------		WAIT FOR 8 ns; -- Time=888 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=900 ns		-- --------------------		WAIT FOR 8 ns; -- Time=908 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=920 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000010010"); --12		-- --------------------		WAIT FOR 8 ns; -- Time=928 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=940 ns		-- --------------------		WAIT FOR 8 ns; -- Time=948 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=960 ns		read_enable_in <= transport '1';		write_enable_in <= transport '0';		write_data_in <= transport std_logic_vector'("000000000000000000000000000000010011"); --13		-- --------------------		WAIT FOR 8 ns; -- Time=968 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=980 ns		-- --------------------		WAIT FOR 8 ns; -- Time=988 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1000 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1008 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1020 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1028 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1040 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1048 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1060 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1068 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1080 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1088 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1100 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1108 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1120 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1128 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1140 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1148 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1160 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1168 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1180 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1188 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1200 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1208 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1220 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1228 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1240 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1248 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1260 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1268 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1280 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1288 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1300 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1308 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1320 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1328 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1340 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1348 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1360 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1368 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1380 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1388 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1400 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1408 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1420 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1428 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1440 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1448 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1460 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1468 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1480 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1488 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1500 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1508 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1520 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1528 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1540 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1548 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1560 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1568 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1580 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1588 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1600 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1608 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1620 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1628 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1640 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1648 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1660 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1668 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1680 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1688 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1700 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1708 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1720 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1728 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1740 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1748 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1760 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1768 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1780 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1788 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1800 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1808 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1820 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1828 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1840 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1848 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1860 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1868 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1880 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1888 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1900 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1908 ns		clock_in <= transport '0';		-- --------------------		WAIT FOR 12 ns; -- Time=1920 ns		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0		-- --------------------		WAIT FOR 8 ns; -- Time=1928 ns		clock_in <= transport '1';		-- --------------------		WAIT FOR 12 ns; -- Time=1940 ns		-- --------------------		WAIT FOR 8 ns; -- Time=1948 ns		-- --------------------		IF (TX_ERROR = 0) THEN 			write(TX_OUT,string'("No errors or warnings"));			writeline(results, TX_OUT);			ASSERT (FALSE) REPORT				"Simulation successful (not a failure).  No problems detected. "				SEVERITY FAILURE;		ELSE			write(TX_OUT, TX_ERROR);			write(TX_OUT, string'(				" errors found in simulation"));			writeline(results, TX_OUT);			ASSERT (FALSE) REPORT				"Errors found during simulation"				SEVERITY FAILURE;		END IF;	END PROCESS;END tb_cc_arch;CONFIGURATION fifoctlr_cc_v2_cfg OF tb_cc IS	FOR tb_cc_arch	END FOR;END fifoctlr_cc_v2_cfg;
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