fifoctlr_cc_tb.vhd

这是一个基于xilinx ISE9.1的一个历程

-- D:\PROJECTS\GOLDEN_SAMPLE_PROJECTS\V2_FIFO_VHD_258\FIFOCTLR_CC_TB.VHD
-- VHDL Test Bench created by HDL Bencher 1.02
-- Mon Feb 05 11:59:49 2001

LIBRARY  ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

LIBRARY  UNISIM;
USE UNISIM.VCOMPONENTS.ALL;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY tb_cc IS
END tb_cc;

ARCHITECTURE tb_cc_arch OF tb_cc IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT fifoctlr_cc_v2
		PORT (
			clock_in : IN  std_logic;
			read_enable_in : IN  std_logic;
			write_enable_in : IN  std_logic;
			write_data_in : IN  std_logic_vector (35 DOWNTO 0);
			fifo_gsr_in : IN  std_logic;
			read_data_out : OUT  std_logic_vector (35 DOWNTO 0);
			full_out : OUT  std_logic;
			empty_out : OUT  std_logic;
			fifocount_out : OUT  std_logic_vector (3 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clock_in : std_logic;
	SIGNAL read_enable_in : std_logic;
	SIGNAL write_enable_in : std_logic;
	SIGNAL write_data_in : std_logic_vector (35 DOWNTO 0);
	SIGNAL fifo_gsr_in : std_logic;
	SIGNAL read_data_out : std_logic_vector (35 DOWNTO 0);
	SIGNAL full_out : std_logic;
	SIGNAL empty_out : std_logic;
	SIGNAL fifocount_out : std_logic_vector (3 DOWNTO 0);

BEGIN
	UUT : fifoctlr_cc_v2
	PORT MAP (
		clock_in => clock_in,
		read_enable_in => read_enable_in,
		write_enable_in => write_enable_in,
		write_data_in => write_data_in,
		fifo_gsr_in => fifo_gsr_in,
		read_data_out => read_data_out,
		full_out => full_out,
		empty_out => empty_out,
		fifocount_out => fifocount_out
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_read_data_out(
			next_read_data_out : std_logic_vector (35 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (read_data_out /= next_read_data_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns read_data_out="));
				write(TX_LOC, read_data_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_read_data_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_full_out(
			next_full_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (full_out /= next_full_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns full_out="));
				write(TX_LOC, full_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_full_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_empty_out(
			next_empty_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (empty_out /= next_empty_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns empty_out="));
				write(TX_LOC, empty_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_empty_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_fifocount_out(
			next_fifocount_out : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (fifocount_out /= next_fifocount_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns fifocount_out="));
				write(TX_LOC, fifocount_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_fifocount_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		clock_in <= transport '0';
		read_enable_in <= transport '0';
		write_enable_in <= transport '0';
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0
		fifo_gsr_in <= transport '1';
		-- --------------------
		WAIT FOR 8 ns; -- Time=8 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=20 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=28 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=40 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=48 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=60 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=68 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=80 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=88 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=100 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=108 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=120 ns
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 8 ns; -- Time=128 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=140 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=148 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=160 ns
		write_enable_in <= transport '1';
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 8 ns; -- Time=168 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=180 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=188 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=200 ns
		write_enable_in <= transport '1';
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000000"); --0
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 8 ns; -- Time=208 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=220 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=228 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=240 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000001"); --1
		-- --------------------
		WAIT FOR 8 ns; -- Time=248 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=260 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=268 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=280 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000010"); --2
		-- --------------------
		WAIT FOR 8 ns; -- Time=288 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=300 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=308 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=320 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000011"); --3
		-- --------------------
		WAIT FOR 8 ns; -- Time=328 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=340 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=348 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=360 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000100"); --4
		-- --------------------
		WAIT FOR 8 ns; -- Time=368 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=380 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=388 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=400 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000101"); --5
		-- --------------------
		WAIT FOR 8 ns; -- Time=408 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=420 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=428 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=440 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000110"); --6
		-- --------------------
		WAIT FOR 8 ns; -- Time=448 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=460 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=468 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=480 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000000111"); --7
		-- --------------------
		WAIT FOR 8 ns; -- Time=488 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=500 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=508 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=520 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001000"); --8
		-- --------------------
		WAIT FOR 8 ns; -- Time=528 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=540 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=548 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=560 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001001"); --9
		-- --------------------
		WAIT FOR 8 ns; -- Time=568 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=580 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=588 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=600 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001010"); --A
		-- --------------------
		WAIT FOR 8 ns; -- Time=608 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=620 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=628 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=640 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001011"); --B
		-- --------------------
		WAIT FOR 8 ns; -- Time=648 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=660 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=668 ns
		clock_in <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=680 ns
		write_data_in <= transport std_logic_vector'("000000000000000000000000000000001100"); --C
		-- --------------------
		WAIT FOR 8 ns; -- Time=688 ns
		clock_in <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=700 ns
		-- --------------------
		WAIT FOR 8 ns; -- Time=708 ns
		clock_in <= transport '0';