untitled2.tdf

多功能数字钟的设计

library ieee;
use ieee.std_logic_1164.all;
entity fen40 is 
   port(clk:in std_logic;
          q:out std_logic);
end;
architecture arc of fen40 is
  begin
  process(clk)
    begin
    variable cnt:integer range 0 to 39;
    begin
     if clk'event and clk='1' then
          if cnt<39 then
            cnt:=cnt+1;
            q<='0';
          else cnt:=0;
              q<='1';
          end if;
     end if;
  end process;
end;