scan.vhd

多功能数字钟的设计

library ieee;
use ieee.std_logic_1164.all;
entity scan is
  port(sel:in std_logic_vector(2 downto 0);
       led6:out std_logic_vector(5 downto 0));
end;
architecture hav of scan is
begin 
  process(sel)
  begin
   case sel is
          when "000"=>led6<="111110";
          when "001"=>led6<="111101";
          when "011"=>led6<="111011";
          when "100"=>led6<="110111";
          when "101"=>led6<="101111";
          when "111"=>led6<="011111";
          when others=>led6<="111111";
         end case;
   end process;
end hav;