sel.vhd

来自「多功能数字钟的设计」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sel IS
  PORT(clk: IN STD_LOGIC;
       q: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
end sel;
ARCHITECTURE are OF sel is
BEGIN
  PROCESS(clk)
   VARIABLE cnt:STD_LOGIC_VECTOR(2 DOWNTO 0);
  BEGIN
   IF clk'event AND clk='1' THEN
        cnt:=cnt+1;
   END IF;
        q<=cnt;
    END PROCESS;
END are;