fen10.vhd

来自「多功能数字钟的设计」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
entity fen10 is 
   port(clk:in std_logic;
          q:out std_logic);
end;
architecture arc of fen10 is
  signal n:std_logic;
  begin
  process(clk)
    variable cnt:integer range 0 to 9;
    begin
        if clk'event and clk='1' then
            if cnt<9 then
             cnt:=cnt+1;
             n<='0';
            else cnt:=0;
              n<='1';
           end if;
     end if;
  end process;
     q<=n;
end;