clkk.vhd

来自「多功能数字钟的设计」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
entity clkk is
 port(clk: in std_logic;
     clk500,clklk: out std_logic);
end clkk;
architecture behav of clkk is
  signal x: std_logic;
begin
  process(clk)
  variable cnt: integer range 0 to 1999;
begin
  if clk'event and clk='1' then
   if cnt<1999 then
        cnt:=cnt+1;
   else cnt:=0;
       x<=not x;
   end if;
  end if;
       clklk<=x;
 end process;
 process(x)
  variable y: std_logic;
 begin
  if x'event and x='1' then
    y:=not y;
  end if;
    clk500<=y;
 end process;
end behav;