📄 zhuzimiaobiao.rpt
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Total fan-in: 321/6912 ( 4%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 14
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 98
Total flipflops required: 39
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 6/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 8 0 1 1 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 8 1 1 8 4 0 1 0 0 5 8 8 8 8 0 0 81/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
Total: 8 0 1 1 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 16 1 1 8 4 0 1 0 0 5 8 8 8 8 0 0 98/0
Device-Specific Information: i:\miaobiao\zhuzimiaobiao.rpt
zhuzimiaobiao
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT ^ 0 0 0 25 a
126 - - - -- INPUT G ^ 0 0 0 0 clk
137 - - - 30 INPUT ^ 0 0 0 7 stop
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: i:\miaobiao\zhuzimiaobiao.rpt
zhuzimiaobiao
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
128 - - - 19 OUTPUT 0 1 0 0 led0
130 - - - 22 OUTPUT 0 1 0 0 led1
131 - - - 23 OUTPUT 0 1 0 0 led2
132 - - - 26 OUTPUT 0 1 0 0 led3
133 - - - 28 OUTPUT 0 1 0 0 led4
135 - - - 29 OUTPUT 0 1 0 0 led5
114 - - - 06 OUTPUT 0 1 0 0 q0
113 - - - 05 OUTPUT 0 1 0 0 q1
112 - - - 04 OUTPUT 0 1 0 0 q2
111 - - - 03 OUTPUT 0 1 0 0 q3
110 - - - 02 OUTPUT 0 1 0 0 q4
109 - - - 01 OUTPUT 0 1 0 0 q5
102 - - A -- OUTPUT 0 1 0 0 q6
101 - - A -- OUTPUT 0 0 0 0 q7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: i:\miaobiao\zhuzimiaobiao.rpt
zhuzimiaobiao
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - F 19 SOFT s ! 1 0 0 5 a~1
- 7 - C 21 AND2 0 2 0 1 |CNT60:3|LPM_ADD_SUB:158|addcore:adder|:55
- 5 - C 21 OR2 0 4 0 1 |CNT60:3|LPM_ADD_SUB:158|addcore:adder|:69
- 3 - C 21 DFFE 0 4 0 9 |CNT60:3|:11
- 1 - C 24 DFFE 0 4 0 5 |CNT60:3|cin (|CNT60:3|:13)
- 6 - C 24 DFFE 1 4 0 3 |CNT60:3|cnt03 (|CNT60:3|:16)
- 8 - C 24 DFFE 1 3 0 4 |CNT60:3|cnt02 (|CNT60:3|:17)
- 7 - C 24 DFFE 1 4 0 4 |CNT60:3|cnt01 (|CNT60:3|:18)
- 2 - C 24 DFFE 1 1 0 5 |CNT60:3|cnt00 (|CNT60:3|:19)
- 5 - C 24 AND2 s 0 3 0 1 |CNT60:3|~30~1
- 6 - C 21 DFFE 1 4 0 3 |CNT60:3|cnt13 (|CNT60:3|:128)
- 1 - C 21 DFFE 1 4 0 3 |CNT60:3|cnt12 (|CNT60:3|:129)
- 8 - C 21 DFFE 1 4 0 4 |CNT60:3|cnt11 (|CNT60:3|:130)
- 2 - C 21 DFFE 1 2 0 5 |CNT60:3|cnt10 (|CNT60:3|:131)
- 4 - C 21 AND2 0 4 0 4 |CNT60:3|:147
- 8 - A 21 AND2 0 2 0 1 |CNT60:20|LPM_ADD_SUB:158|addcore:adder|:55
- 5 - A 21 OR2 0 4 0 1 |CNT60:20|LPM_ADD_SUB:158|addcore:adder|:69
- 7 - A 21 DFFE 0 4 0 4 |CNT60:20|cin (|CNT60:20|:13)
- 5 - A 19 DFFE 1 4 0 3 |CNT60:20|cnt03 (|CNT60:20|:16)
- 8 - A 19 DFFE 1 3 0 4 |CNT60:20|cnt02 (|CNT60:20|:17)
- 7 - A 19 DFFE 1 4 0 4 |CNT60:20|cnt01 (|CNT60:20|:18)
- 4 - A 19 DFFE 1 1 0 5 |CNT60:20|cnt00 (|CNT60:20|:19)
- 2 - A 19 AND2 s 0 3 0 1 |CNT60:20|~30~1
- 1 - A 21 DFFE 1 4 0 3 |CNT60:20|cnt13 (|CNT60:20|:128)
- 4 - A 21 DFFE 1 4 0 3 |CNT60:20|cnt12 (|CNT60:20|:129)
- 2 - A 21 DFFE 1 4 0 4 |CNT60:20|cnt11 (|CNT60:20|:130)
- 3 - A 21 DFFE 1 2 0 5 |CNT60:20|cnt10 (|CNT60:20|:131)
- 6 - A 21 OR2 ! 0 4 0 3 |CNT60:20|:147
- 5 - C 34 AND2 0 2 0 1 |CNT90:6|LPM_ADD_SUB:158|addcore:adder|:55
- 8 - C 31 OR2 0 4 0 1 |CNT90:6|LPM_ADD_SUB:158|addcore:adder|:69
- 2 - C 34 DFFE 0 4 0 10 |CNT90:6|:11
- 1 - C 33 DFFE 0 4 0 5 |CNT90:6|cin (|CNT90:6|:13)
- 5 - C 33 DFFE 1 4 0 3 |CNT90:6|cnt03 (|CNT90:6|:16)
- 8 - C 33 DFFE 1 3 0 4 |CNT90:6|cnt02 (|CNT90:6|:17)
- 3 - C 33 DFFE 1 4 0 4 |CNT90:6|cnt01 (|CNT90:6|:18)
- 7 - C 33 DFFE 1 1 0 5 |CNT90:6|cnt00 (|CNT90:6|:19)
- 6 - C 33 AND2 s 0 3 0 1 |CNT90:6|~30~1
- 6 - C 31 DFFE 1 4 0 3 |CNT90:6|cnt13 (|CNT90:6|:128)
- 4 - C 34 DFFE 1 4 0 3 |CNT90:6|cnt12 (|CNT90:6|:129)
- 1 - C 31 DFFE 1 4 0 4 |CNT90:6|cnt11 (|CNT90:6|:130)
- 8 - C 34 DFFE 1 2 0 5 |CNT90:6|cnt10 (|CNT90:6|:131)
- 5 - C 31 AND2 0 4 0 4 |CNT90:6|:147
- 2 - C 06 AND2 0 4 0 4 |DISP:32|:390
- 3 - C 06 OR2 ! 0 4 0 4 |DISP:32|:402
- 8 - C 06 OR2 s 0 4 0 1 |DISP:32|~437~1
- 1 - C 06 OR2 0 4 1 0 |DISP:32|:438
- 7 - C 01 OR2 0 3 0 1 |DISP:32|:464
- 1 - C 01 OR2 0 4 1 0 |DISP:32|:473
- 8 - C 01 OR2 0 4 1 0 |DISP:32|:506
- 3 - C 01 OR2 0 4 0 1 |DISP:32|:525
- 1 - C 03 OR2 0 4 1 0 |DISP:32|:539
- 7 - C 04 OR2 0 4 1 0 |DISP:32|:572
- 7 - C 06 OR2 0 4 0 1 |DISP:32|:588
- 6 - C 06 AND2 0 4 1 0 |DISP:32|:605
- 5 - C 06 OR2 0 4 0 1 |DISP:32|:624
- 4 - C 01 OR2 s 0 3 0 3 |DISP:32|~635~1
- 4 - C 06 OR2 0 4 1 0 |DISP:32|:638
- 1 - C 32 OR2 ! 0 2 0 2 |FEN40:1|LPM_ADD_SUB:68|addcore:adder|:67
- 7 - C 31 AND2 0 2 0 1 |FEN40:1|LPM_ADD_SUB:68|addcore:adder|:75
- 6 - C 32 OR2 0 4 0 1 |FEN40:1|LPM_ADD_SUB:68|addcore:adder|:95
- 2 - C 31 DFFE + 1 1 0 10 |FEN40:1|n (|FEN40:1|:4)
- 7 - C 32 DFFE + 1 2 0 2 |FEN40:1|cnt5 (|FEN40:1|:5)
- 3 - C 31 DFFE + 1 2 0 2 |FEN40:1|cnt4 (|FEN40:1|:6)
- 4 - C 31 DFFE + 1 2 0 3 |FEN40:1|cnt3 (|FEN40:1|:7)
- 5 - C 32 DFFE + 1 2 0 1 |FEN40:1|cnt2 (|FEN40:1|:8)
- 4 - C 32 DFFE + 1 2 0 1 |FEN40:1|cnt1 (|FEN40:1|:9)
- 3 - C 32 DFFE + 1 1 0 2 |FEN40:1|cnt0 (|FEN40:1|:10)
- 2 - C 32 OR2 0 4 0 7 |FEN40:1|:24
- 8 - C 32 OR2 0 2 0 4 |FEN40:1|:39
- 3 - A 19 OR2 0 4 0 1 |MUX24:5|:190
- 3 - C 25 OR2 0 3 0 1 |MUX24:5|:200
- 5 - C 01 OR2 0 3 0 1 |MUX24:5|:210
- 6 - C 01 OR2 0 3 0 1 |MUX24:5|:220
- 2 - C 01 OR2 0 3 0 11 |MUX24:5|:230
- 1 - A 19 OR2 ! 0 4 0 1 |MUX24:5|:239
- 2 - C 25 OR2 ! 0 3 0 1 |MUX24:5|:242
- 3 - C 24 OR2 ! 0 3 0 1 |MUX24:5|:245
- 3 - C 34 OR2 ! 0 3 0 1 |MUX24:5|:248
- 4 - C 33 OR2 ! 0 3 0 11 |MUX24:5|:251
- 6 - A 19 OR2 ! 0 4 0 1 |MUX24:5|:260
- 1 - C 25 OR2 ! 0 3 0 1 |MUX24:5|:263
- 4 - C 24 OR2 ! 0 3 0 1 |MUX24:5|:266
- 3 - C 19 OR2 ! 0 3 0 1 |MUX24:5|:269
- 2 - C 19 OR2 ! 0 3 0 11 |MUX24:5|:272
- 1 - C 30 OR2 ! 0 4 0 1 |MUX24:5|:281
- 6 - C 34 OR2 ! 0 3 0 1 |MUX24:5|:284
- 7 - C 34 OR2 ! 0 3 0 1 |MUX24:5|:287
- 1 - C 34 OR2 ! 0 3 0 1 |MUX24:5|:290
- 2 - C 33 OR2 ! 0 3 0 9 |MUX24:5|:293
- 5 - C 30 OR2 ! 0 3 1 4 |SCAN:4|:149
- 4 - C 27 OR2 ! 0 3 1 4 |SCAN:4|:159
- 4 - C 25 OR2 ! 0 3 1 4 |SCAN:4|:169
- 2 - C 23 OR2 ! 0 3 1 4 |SCAN:4|:179
- 1 - C 22 OR2 ! 0 3 1 4 |SCAN:4|:189
- 1 - C 19 OR2 ! 0 3 1 4 |SCAN:4|:199
- 4 - C 30 DFFE + 0 2 0 6 |SEL:31|cnt2 (|SEL:31|:5)
- 2 - C 30 DFFE + 0 1 0 7 |SEL:31|cnt1 (|SEL:31|:6)
- 3 - C 30 DFFE + 0 0 0 8 |SEL:31|cnt0 (|SEL:31|:7)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: i:\miaobiao\zhuzimiaobiao.rpt
zhuzimiaobiao
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/144( 1%) 1/ 72( 1%) 7/ 72( 9%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 24/144( 16%) 5/ 72( 6%) 23/ 72( 31%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: i:\miaobiao\zhuzimiaobiao.rpt
zhuzimiaobiao
** CLOCK SIGNALS **
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