tone.vhd

在FPGA上实现声卡接口

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Tone IS
    PORT ( Index :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
           CODE  : OUT INTEGER RANGE 0 TO 15;
           HIGH  : OUT STD_LOGIC; 
           Tone  : OUT INTEGER RANGE 0 TO 16#7FF#  );
END;
ARCHITECTURE one OF Tone IS
BEGIN
    Search : PROCESS(Index)
    BEGIN
      CASE Index IS          -- 译码电路，查表方式，控制音调的预置数
        WHEN "00000001"  => Tone <= 773;  CODE <= 1; HIGH <= '0';  
        WHEN "00000010"  => Tone <= 912;  CODE <= 2; HIGH <= '0';  
        WHEN "00000100"  => Tone <= 1036; CODE <= 3; HIGH <= '0'; 
        WHEN "00001000"  => Tone <= 1116; CODE <= 4; HIGH <= '0'; 
        WHEN "00010000"  => Tone <= 1197; CODE <= 5; HIGH <= '0';  
        WHEN "00100000"  => Tone <= 1290; CODE <= 6; HIGH <= '0';  
        WHEN "01000000"  => Tone <= 1372; CODE <= 7; HIGH <= '0';  
        WHEN "10000000"  => Tone <= 1410; CODE <= 1; HIGH <= '1';  
        WHEN   OTHERS    => Tone <= 2047; CODE <= 0; HIGH <= '0';  
        END CASE;
    END PROCESS;
END;