xd_lcd240128.v

一款240＊128的LCD模块在ALTERA FPGA NIOS中的应用

/****************************************Copyright (c)**************************************************
**                               张敏　西北核技术研究所一室　2008
**
**--------------File Info-------------------------------------------------------------------------------
** File name:			xd_lcd240128.v
** Last modified Date:	2008-7-30
** Last Version:		1.0
** Descriptions:		xd_lcd240128控制逻辑
**------------------------------------------------------------------------------------------------------
** Created by:			张敏　西北核技术研究所一室
** Created date:		2008-7-30
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module xd_lcd240128_interface(
	//模块输入
	clk,
	reset_n,
	chipselect,
	write,
	address,
	writedata,
	
	//模块输出
	lcd_wr,
	lcd_rd,
	lcd_ce,
	lcd_cd,
	lcd_rst,
	lcd_data	//lcd 数据线
	
	);

//Inputs
input clk;			//Input Clock
input reset_n;		//Reset
input chipselect;	//Avalon Chip select signal
input write;		//Avalon read signal
input [1:0] address;//Avalon Address bus 
input [7:0] writedata;//Avalon ritedata
	

//Outputs
output lcd_wr;			//lcd 写线
output lcd_rd;			//lcd 读线
output lcd_ce;			//lcd 使能线
output lcd_cd;			//lcd 指令、数据控线
output lcd_rst;			//lcd rst
output reg [7:0] lcd_data;//lcd 数据线

//中间寄存器声明
reg lcd_wr_r;			//lcd wr
//reg lcd_rd_r;			//lcd rd
reg lcd_cd_r;			//lcd cd
reg lcd_rst_r;			//lcd rst
reg [3:0] timecount;	//状态机状态变量
	
//寄存器输出
assign lcd_ce = 1'h0;	//直接将LCD ce 置0，即一直使能
assign lcd_rd = 1'h1;	//直接将LCD rd 置1，即一直不用读

assign lcd_wr = lcd_wr_r;
//assign lcd_rd = lcd_rd_r;
assign lcd_cd = lcd_cd_r;
assign lcd_rst = lcd_rst_r;

//初始化状态
initial
begin
	lcd_wr_r<= 1'h1;
	lcd_cd_r<= 1'h1;
	lcd_rst_r<= 1'h1;
	timecount = 4'h0;
end

//合成写控制
wire	write_act;
assign	write_act  = chipselect & write ;


parameter tcntwritemax = 4'ha;//写LCD比较耗时，一般需要用到55个时钟周期约550ns
//write
always @(posedge clk )
begin
	if (write_act )//AVALON　写数据、指令、重启LCD
	begin
		if (address ==2'h0  )//写指令// CD、RD、WR三位，C/D高指令,RD、WR低有效
		begin
				if(timecount==4'h0)//
				begin
					lcd_wr_r<= 0;//写入
					lcd_cd_r<= 1;//指令
					lcd_data<=writedata;//将指令输出到LCD的数据线
				end
				else if(timecount>=4'h0 && timecount<=tcntwritemax)
				begin
				end
				else//第11个时钟周期更改RD、WR,以100M计地址、数据的建立时间约110ns，符合100ns的最小要求
				begin
					lcd_wr_r<= 1;//不写入
					timecount = 4'h0;
				end
    			if(timecount<=tcntwritemax&&timecount>=0)  begin  timecount = timecount+1;  end
				else  begin  timecount =0; end
		end
		else if (address ==2'h1 )//写数据// CD、RD、WR三位，C/D高指令,RD、WR低有效
		begin
				if(timecount==4'h0)//
				begin
					lcd_wr_r<= 0;//写入
					lcd_cd_r<= 0;//数据
					lcd_data<=writedata;//将数据输出到LCD的数据线
				end
				else if(timecount>=4'h0 && timecount<=tcntwritemax)
				begin
				end
				else//第11个时钟周期更改RD、WR,以100M计地址、数据的建立时间约110ns，符合100ns的最小要求
				begin
					lcd_wr_r<= 1;//不写入
					timecount = 4'h0;
				end
    			if(timecount<=tcntwritemax&&timecount>=0)  begin  timecount = timecount+1;  end
				else  begin  timecount =0; end
		end
		else if (address ==2'h2 )//重启// CD、RD、WR三位，C/D高指令,RD、WR低有效
		begin
				//使用方法为：RESET_LCM240128(base,0),100ms后再RESET_LCM240128(base,1)
				lcd_rst_r <= writedata[0];
		end
		else//非法地址，将各路信号置为默认状态
		begin
			lcd_wr_r<= 1;//不写入
			timecount = 4'h0;
		end
	end
	else//非写时，将各路信号置为默认状态
	begin
		lcd_wr_r<= 1;//不写入
		timecount = 4'h0;
	end
end



endmodule