adc5540_task_logic.v

周立功出的smartsopc开发件中模数转换 adc5540模块

/****************************************Copyright (c)**************************************************
**                               张敏　西北核技术研究所一室　2008
**
**--------------File Info-------------------------------------------------------------------------------
** File name:			adc5540_task_logic.v
** Last modified Date:	2008-7-26
** Last Version:		2.0
** Descriptions:		ad Tlc5540控制IP的逻辑描述
**------------------------------------------------------------------------------------------------------
** Created by:			张敏　西北核技术研究所一室
** Created date:		2008-7-25
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module adc5540_task_logic(
	//模块输入
	reset_n,
	clk,
	chipselect,
	address,
	read,
	ad_input,
	//模块输出
	readdata,
	ad_clk,
	ad_noe,
	irq
	);

//Inputs
input reset_n;				//Reset
input clk;					//Input Clock
input chipselect;			//Avalon Chip select signal
input address;	     		//Avalon Address bus 
input read;			    	//Avalon read signal
input [7:0] ad_input;		//AD输出
	

//Outputs
output [7:0] readdata;	//IP的输出，AD采样值
output ad_clk;			//ad control
output ad_noe;			//ad control
output irq;				//intrupt output

//中间寄存器声明
reg [7:0] read_data_r;	//ad output register
reg ad_clk_r;			//ad output register
reg ad_noe_r;			//ad output register
reg irq_r;				//ad output register
reg [3:0] timecount;	//状态机状态变量
	
//寄存器输出
assign readdata = read_data_r;
assign ad_clk = ad_clk_r;
assign ad_noe = ad_noe_r;
assign irq = irq_r;

//初始化状态
initial
begin
	read_data_r<=8'h0;
	ad_clk_r<= 1'h1;
	ad_noe_r<= 1'h1;
	irq_r<= 1'h0;
	timecount = 4'h0;
end

//合成读控制
wire	read_act;
assign	read_act  = chipselect & read;


//read
always @(posedge clk)
begin
	if (read_act && address==0)
	begin
		if(timecount==4'h0)//输出clk下降沿
		begin
			ad_clk_r= 0;
			ad_noe_r= 0;
		end
		else if(timecount==4'h3)//输出clk上升沿
		begin
			ad_clk_r= 1;
		end
		else if(timecount==4'h6)//可以输出数据了,输出中断，提示应用程序采样完成
		begin
			read_data_r <= ad_input;
			irq_r= 1;
		end
		else if(timecount>=4'h0 && timecount<=4'h6)
		begin
		end
		else
		begin
			read_data_r<=8'h0;
			ad_clk_r= 1;
			ad_noe_r= 1;
			irq_r= 0;
		end
    	if(timecount<=6&&timecount>=0)  begin  timecount = timecount+1;  end
		else  begin  timecount =0; end
	end
	else
	begin
		read_data_r<=8'h0;
		ad_clk_r<= 1'h1;
		ad_noe_r<= 1'h1;
		irq_r<= 1'h0;
		timecount = 4'h0;
	end
end



endmodule