📄 control.psm
字号:
; faster presence pulse of overdrive mode can not be detected.
;
; The carry flag will be set if no valid presence pulse was received (wire remained High) and
; can be used to indicate an initialisation failure or success.
;
; The routine only completes 300us after the presence pulse to ensure the DS2432 has
; completed the presence pulse and is ready for the first operation.
;
; Registers used s0,s1,s2
;
DS_init_regular_mode: LOAD s0, 00 ;transmit reset pulse
OUTPUT s0, DS_wire_out_port
;Delay of 500us is equivalent to 12500 instructions at 50MHz.
;This delay loop is formed of 28 instructions requiring 446 repetitions.
LOAD s2, 01 ;[s3,s2]=445 decimal (01BD hex)
LOAD s1, BD
rm_wait_500us: CALL delay_1us ;25 instructions including CALL
SUB s1, 01 ;decrement delay counter
SUBCY s2, 00
JUMP NC, rm_wait_500us ;repeat until -1
LOAD s0, 01 ;end of regular reset pulse
OUTPUT s0, DS_wire_out_port
;Delay of 60us is equivalent to 1500 instructions at 50MHz.
;This delay and is formed of 27 instructions requiring 56 repetitions.
LOAD s1, 38 ;56 (38 hex)
rm_wait_60us: CALL delay_1us ;25 instructions including CALL
SUB s1, 01 ;decrement delay counter
JUMP NZ, rm_wait_60us ;repeat until zero
;The DS_wire is now checked at approximately 1us intervals for the next 240us looking
;to detect an active Low presence pulse. The 240us is equivalent to 6000 instructions
;at 50MHz and this polling loop is formed of 33 instructions requiring 182 repetitions.
LOAD s2, 01 ;set bit which will be reset by a presence pulse
LOAD s1, B6 ;182 (B6 hex)
rm_poll_240us: CALL delay_1us ;25 instructions including CALL
CALL read_DS_wire ;read wire - 5 instructions including CALL
AND s2, s0 ;clear flag if DS_wire was Low
SUB s1, 01 ;decrement delay counter
JUMP NZ, rm_poll_240us ;repeat until zero
TEST s2, 01 ;set carry flag if no pulse detected
RETURN
;
;
;**************************************************************************************
; Read the DS_wire
;**************************************************************************************
;
; The DS_wire signal is read and returned in bit0 of register 's0'.
; Additionally the carry flag is set if the signal is High and reset if Low
;
; Registers used s0
;
read_DS_wire: INPUT s0, DS_wire_in_port
AND s0, DS_wire ;ensure only bit0 is active
TEST s0, DS_wire ;set carry flag if DS_wire is High
RETURN
;
;
;
;**************************************************************************************
; Write a byte to DS2432 in regular speed mode.
;**************************************************************************************
;
; Bytes are written to the DS2432 with LSB first.
;
; The byte to be written should be provided in register 's3' and this will be preserved.
;
; Registers used s0,s1,s2,s3
;
write_byte_slow: LOAD s2, 08 ;8 bits to transmit
wbs_loop: RR s3 ;test next bit LSB first
JUMP C, wbs1 ;transmit '0' or '1'
CALL write_Low_slow
JUMP next_slow_bit
wbs1: CALL write_High_slow
next_slow_bit: SUB s2, 01 ;count bits
JUMP NZ, wbs_loop ;repeat until 8-bits transmitted
RETURN
;
;
;
;**************************************************************************************
; Write a '0' to DS_wire in regular speed mode.
;**************************************************************************************
;
; To write a '0' to the DS_wire the signal must be Low for 60 to 120us. This design
; generates a 78us active Low pulse.
;
; The DS2432 then requires at least 1us of recovery time for which this routine
; provides a 2us delay such that the entire write Low process (slot time) is 80us.
; A recovery time of 1us was also found to be marginal in practice probably due
; to the rise time of the DS_wire via the external pull up resistor.
;
; Registers used s0,s1
;
write_Low_slow: LOAD s0, 00 ;transmit Low pulse
OUTPUT s0, DS_wire_out_port
;Delay of 78us is equivalent to 1950 instructions at 50MHz.
;This delay loop is formed of 27 instructions requiring 72 repetitions.
LOAD s1, 48 ;72 (48 hex)
wls_wait_78us: CALL delay_1us ;25 instructions including CALL
SUB s1, 01 ;decrement delay counter
JUMP NZ, wls_wait_78us ;repeat until zero
LOAD s0, 01 ;end of Low pulse
OUTPUT s0, DS_wire_out_port
CALL delay_1us ;2us recovery time
CALL delay_1us
RETURN
;
;
;**************************************************************************************
; Write a '1' to DS_wire in regular speed mode.
;**************************************************************************************
;
; To write a '1' to the DS_wire the signal must be Low for 1 to 15us to instigate the
; write of the data. This design generates an 8us active Low pulse for this purpose.
;
; Then the output must be High for 53 to 114us to provide the '1' for the DS2432 to
; read and then provide recovery time. This design implements a 72us delay such that
; the entire write High process (slot time) is 80us
;
; Registers used s0,s1
;
write_High_slow: LOAD s0, 00 ;transmit Low pulse
OUTPUT s0, DS_wire_out_port
;Delay of 8us is equivalent to 200 instructions at 50MHz.
;This delay loop is formed of 27 instructions requiring 8 repetitions.
LOAD s1, 08 ;8 (08 hex)
whs_wait_8us: CALL delay_1us ;25 instructions including CALL
SUB s1, 01 ;decrement delay counter
JUMP NZ, whs_wait_8us ;repeat until zero
LOAD s0, 01 ;end of Low pulse
OUTPUT s0, DS_wire_out_port
;Delay of 72us is equivalent to 1800 instructions at 50MHz.
;This delay loop is formed of 27 instructions requiring 67 repetitions.
LOAD s1, 43 ;67 (43 hex)
whs_wait_72us: CALL delay_1us ;25 instructions including CALL
SUB s1, 01 ;decrement delay counter
JUMP NZ, whs_wait_72us ;repeat until zero
RETURN
;
;
;
;**************************************************************************************
; Read a byte from DS2432 in regular speed mode.
;**************************************************************************************
;
; Bytes are read from the DS2432 with LSB first.
;
; The byte read will be returned in register 's3'.
;
; Registers used s0,s1,s2,s3
;
read_byte_slow: LOAD s2, 08 ;8 bits to receive
rbs_loop: CALL read_bit_slow ;read next bit LSB first
SUB s2, 01 ;count bits
JUMP NZ, rbs_loop ;repeat until 8-bits received
RETURN
;
;
;
;
;**************************************************************************************
; Read a data bit sent from the DS2432 in regular speed mode.
;**************************************************************************************
;
; To read a bit, PicoBlaze must initiate the processed with an active Low pulse of
; 1 to 15us. This design generates a 4us active Low pulse for this purpose.
;
; Then DS2432 responds to the Low pulse by diving DS_wire in two differet ways
; depending on the logic level it is trying to send back.
;
; For a logic '0' the DS2432 will drive the DS-wire Low for up to 15us after
; the start of the instigating pulse. Therefore PicoBlaze must read the DS-wire
; before this time has elapsed but only after it has itself released the wire.
;
; For a logic '1' the DS2432 will do nothing and hence the DS-wire will be pulled
; High by the external resistor after PicoBlaze has released the wire. PicoBlaze
; will sample the wire and detect the High level.
;
; In this design, PicoBlaze needs to detect the logic state of the wire after
; releasing the wire at 4us. Sampling the wire too quickly would not provide
; adequate time for a High signal to be formed by the pull up resistor. However, it
; must sample the wire before 15us have elapsed and any potential Low is removed.
; This design samples the wire at 12us which is 8us after the initiation pulse ends.
;
; A further delay of 68us is then allowed for the DS2432 to stop transmitting and
; to recover. This also mean that the entire read process (slot time) is 80us.
;
; The received data bit is SHIFTED into the MSB of register 's3'. In this way
; the reception of 8-bits will shift the first bit into the LSB position of 's3'.
;
; Registers used s0,s1,s3
;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -