fg_ctrl.rmh

来自「和picoblaze完全兼容的mcu ip core」· RMH 代码 · 共 1,476 行 · 第 1/5 页

// #57: CONSTANT(LCD_DB7,128) ;                      Data DB7 - bit7
// #58: ;
// #59: ;
// #60: CONSTANT(LCD_input_port,1) ;LCD character module input data
// #61: CONSTANT(LCD_read_DB4,16) ;    4-bit           Data DB4 - bit4
// #62: CONSTANT(LCD_read_DB5,32) ;    interface       Data DB5 - bit5
// #63: CONSTANT(LCD_read_DB6,64) ;                    Data DB6 - bit6
// #64: CONSTANT(LCD_read_DB7,128) ;                    Data DB7 - bit7
// #65: ;
// #66: ;
// #67: ;
// #68: ;DDS control ports
// #69: ;
// #70: ;DDS control word is 32-bits
// #71: ;
// #72: CONSTANT(DDS_control0_port,2) ; dds_control_word(7:0)
// #73: CONSTANT(DDS_control1_port,4) ; dds_control_word(15:8)
// #74: CONSTANT(DDS_control2_port,8) ; dds_control_word(23:16)
// #75: CONSTANT(DDS_control3_port,16) ; dds_control_word(31:24)
// #76: ;
// #77: ;Frequency scaling control word is 5-bits
// #78: ;
// #79: CONSTANT(DDS_scaling_port,32) ; dds_scaling_word(4:0)
// #80: ;
// #81: ;
// #82: ;**************************************************************************************
// #83: ;Special Register usage
// #84: ;**************************************************************************************
// #85: ;
// #86: ;**************************************************************************************
// #87: ;Scratch Pad Memory Locations
// #88: ;**************************************************************************************
// #89: ;
// #90: CONSTANT(rotary_status,0) ;Status of rotary encoder
// #91: CONSTANT(rotary_event,128) ;  flag set by interrupt in 'rotary_status' - bit7
// #92: ;
// #93: CONSTANT(ISR_preserve_s0,1) ;Preserve s0 contents during ISR
// #94: ;
// #95: CONSTANT(LED_pattern,2) ;LED pattern used in rotation mode
// #96: ;
// #97: ;
// #98: ;BCD digits representing selected and displayed frequency
// #99: ;
// #100: CONSTANT(BCD_digit0,3) ; value           1
// #101: CONSTANT(BCD_digit1,4) ;                10
// #102: CONSTANT(BCD_digit2,5) ;               100
// #103: CONSTANT(BCD_digit3,6) ;             1,000
// #104: CONSTANT(BCD_digit4,7) ;            10,000
// #105: CONSTANT(BCD_digit5,8) ;           100,000
// #106: CONSTANT(BCD_digit6,9) ;         1,000,000
// #107: CONSTANT(BCD_digit7,10) ;        10,000,000
// #108: CONSTANT(BCD_digit8,11) ;       100,000,000
// #109: ;
// #110: ;
// #111: ;Binary integer representation of BCD value
// #112: ;
// #113: CONSTANT(frequency0,12) ;LS byte
// #114: CONSTANT(frequency1,13)
// #115: CONSTANT(frequency2,14)
// #116: CONSTANT(frequency3,15) ;MS byte
// #117: ;
// #118: ;
// #119: ;Control of frequency selection values
// #120: ;
// #121: CONSTANT(cursor_position,16) ; Pointer to edit position on LCD
// #122: CONSTANT(edit_digit_pointer,17) ; BCD digit to be changed
// #123: ;
// #124: ;
// #125: ;
// #126: ;80-bit product resulting from 32-bit frequency x 48-bit scaling constant
// #127: ;
// #128: CONSTANT(product0,18) ;LS byte
// #129: CONSTANT(product1,19)
// #130: CONSTANT(product2,20)
// #131: CONSTANT(product3,21)
// #132: CONSTANT(product4,22)
// #133: CONSTANT(product5,23)
// #134: CONSTANT(product6,24)
// #135: CONSTANT(product7,25)
// #136: CONSTANT(product8,26)
// #137: CONSTANT(product9,27) ;MS byte
// #138: ;
// #139: ;Local copies of the DDS control word and DDS scaling word
// #140: ;
// #141: CONSTANT(DDS_control0,28) ; dds_control_word(7:0)
// #142: CONSTANT(DDS_control1,29) ; dds_control_word(15:8)
// #143: CONSTANT(DDS_control2,30) ; dds_control_word(23:16)
// #144: CONSTANT(DDS_control3,31) ; dds_control_word(31:24)
// #145: CONSTANT(DDS_scaling,32) ; dds_scaling_word(4:0)
// #146: ;
// #147: ;**************************************************************************************
// #148: ; Useful data constants
// #149: ;**************************************************************************************
// #150: ;
// #151: ; To convert the frequency into a DDS control value a high precision scaling
// #152: ; factor is used. This is a 48-bit number which converts the frequency presented
// #153: ; as an 32-bit integer into the 32-bit value required by the phase accumulator
// #154: ; to synthesize the desired frequency. The scaling factor is derived using the
// #155: ; following method. First I will consider the scaling factor which results in the
// #156: ; desired frequency being generated directly at the output of the phase accumulator
// #157: ; which is suitable for low frequencies in which a few ns of jitter is acceptable.
// #158: ;
// #159: ; 'Fpa' is frequency generated by the MSB of the phase accumulator.
// #160: ; 'p' is number of phase accumulator which in this case is 32 bits.
// #161: ; 'clk' is the input clock frequency to the phase accumulator which is 200MHz.
// #162: ; 'N' is the DDS control word value which is also 'p' bits (32 in this case).
// #163: ;
// #164: ; Frequency at MSB of phase accumulator is then
// #165: ;
// #166: ;       Fpa = clk x N / (2^p)
// #167: ;
// #168: ; Note that the maximum value allowed for 'N' is (2^p)/2 which results in Fpa=clk/2.
// #169: ;  for 'N' greater than that value 'Fpa' would decrease in frequency (aliasing).
// #170: ;
// #171: ;
// #172: ; By simple reorganisation of the equation we can compute 'N'
// #173: ;
// #174: ;       N = Fpa x (2^p) / clk
// #175: ;
// #176: ;
// #177: ; Now it is easier to approach the next step using specific example.
// #178: ;
// #179: ; So for a frequency of Fpa = 1MHz then
// #180: ;       N = 1MHz x (2^32)/200MHz = 21474836.48
// #181: ;
// #182: ; We must use the nearest 32-bit integer value 21474836 and this in turn
// #183: ; is best viewed as the 32-bit hexadecimal value 0147AE14.
// #184: ;
// #185: ; In this case the value we have to work with is a 32-bit integer frequency
// #186: ; value of 1 million which is 000F4240.
// #187: ;
// #188: ; So now we need to translate the value 000F4240 into 0147AE14. This is
// #189: ; where a 48-bit scaling value is used together with a full precision multiplier
// #190: ; as this ensures adequate accuracy of the final frequency.
// #191: ;
// #192: ;        32-bit frequency value                  ffffffff
// #193: ;        48-bit scaling value              x ssssssssssss
// #194: ;                                    --------------------
// #195: ;        80-bit product              nnnnnnnnnnnnnnnnnnnn
// #196: ;
// #197: ; The art is to organise the scaling factor into the range where the most is made of
// #198: ; the 48-bit resolution available but which will result in the correct 32-bit output.
// #199: ; The way this is achieved is the select an appropriate 32-bits from the available 80-bit
// #200: ; product for use as 'N' and truncate 'y' least significant bits.
// #201: ;
// #202: ; From this we can deduce that for a target frequency 'Ft' at the input then the
// #203: ; scaling value 'S' is given by
// #204: ;
// #205: ;    S = N x (2^y) / Ft    with the condition that S < 2^48 but as large as possible
// #206: ;
// #207: ; For best accuracy we calculate 'S' using the full precision value of 'N' divided
// #208: ; by Ft and then multiply continuously by 2 until we reach the biggest value less
// #209: ; that 2^48. The number of multiplications by 2 indicating the value of 'y'.
// #210: ;
// #211: ; In this case we find that 'y' is 43.....
// #212: ;       S = 21474836.48 x (2^43) / 1000000 = 21.47483648 x (2^43)
// #213: ;                                          = 188894659314785.80854784
// #214: ;
// #215: ;  ...round to nearest integer and convert to hexadecimal S = ABCC77118462
// #216: ;
// #217: ; N will be taken from the 80 bit product by removing the 43 LSBs and the 5 MSBs
// #218: ; to leave the 32 active bits required. This is best achieved by shifting left
// #219: ; by 5 places (multiply by 2^5=32) and keeping the upper 32-bits.
// #220: ;
// #221: ;
// #222: ; Sanity check....
// #223: ;   Note that most calculators do not support >64 bit values to you will either
// #224: ;   need to decompose your calculation and perform some of it manually or trust
// #225: ;   the PicoBlaze implementation :-)
// #226: ;
// #227: ;     Ft = 1MHz =                         000F4240
// #228: ;             S =                  x  ABCC77118462
// #229: ;                             --------------------
// #230: ;                             000A3D70A3D70A405C80
// #231: ;
// #232: ;     shift left 5 places                     x 20
// #233: ;                             --------------------
// #234: ;                             0147AE147AE1480B9000
// #235: ;
// #236: ; As expected, the most significant 32-bit (4 bytes) are 0147AE14 hex which is
// #237: ; the DDS control word for 1MHz calculated previously.
// #238: ;
// #239: ; ***
// #240: ;
// #241: ; Now I will consider how this needs to be modified for the circuit presented
// #242: ; which has a second DCM connected to the output of the phase accumulator to
// #243: ; multiply the synthesized frequency and reduce cycle to cycle jitter at
// #244: ; the same time. There is then a clock divider circuit connected to the output
// #245: ; of the DCM which allows lower frequencies to be formed a different way (more of
// #246: ; that later). As a minimum that divider circuit will divide by 2 which ensures that
// #247: ; a square wave is presented to the clocked put pin. So in this circuit the fundamental
// #248: ; multiplication factor is 8 formed by a 16 times multiplication by the DCM (256/16) and
// #249: ; then a divide by 2.
// #250: ;
// #251: ; The overall multiplication factor of this sebsequent circuit means that for final
// #252: ; output from the DCM to be the desired frequency, the output from the phase accumulator
// #253: ; needs to be the same number of times smaller. This is not a bad thing because the
// #254: ; percentage jitter of waveforms produced by the phase accumulator is better for lower
// #255: ; frequencies made from more clock cycles.
// #256: ;
// #257: ; So we modify the basic equation to
// #258: ;
// #259: ;    Fout = Frequency at output of DCM
// #260: ;       M = Multiplying factor of DCM
// #261: ;
// #262: ;    Fout = M x Fpa = M x clk x N / (2^p)
// #263: ;
// #264: ;
// #265: ; By simple reorganisation of the equation we can compute 'N'
// #266: ;
// #267: ;       N = Fout x (2^p) / (clk x M)
// #268: ;
// #269: ;
// #270: ; In this design M=8, p=32, clk=200MHz
// #271: ;
// #272: ; So now consider generating a nominal maximum frequency of 100MHz which will require
// #273: ; the frequency synthesized by the phase accumulator to be 12.5MHz.
// #274: ;
// #275: ;       N = 100MHz x (2^32) / (200MHz x 8) = 268435456 = 10000000 Hex
// #276: ;
// #277: ; This all seems like a very convenient number but it simply reflects that 12.5MHz
// #278: ; is a perfect division of the 200MHz clock and that that output from the phase
// #279: ; accumulator will be formed perfectly of 16 of the 200MHz clock periods every time
// #280: ; (8 Low and 8 High) with no additional jitter.
// #281: ;
// #282: ; So now we work out the scaling factor with the same rules as used previously that
// #283: ; the scaling factor should be as large as possible within the 48-bits allocated.
// #284: ;
// #285: ;    S = N x (2^y) / Ft    with the condition that S < 2^48 but as large as possible
// #286: ;
// #287: ; In this case Ft = 100MHz = 055FE100 and the biggest value for S is found when using
// #288: ; y=46
// #289: ;
// #290: ;    S = 268435456 x (2^46) / 100000000 = 2.68435456 x (2^46)
// #291: ;                                       = 188894659314785.80854784
// #292: ;
// #293: ;      round to 188894659314786  = ABCC77118462
// #294: ;
// #295: ; Actually this is the exact same scaling constant as previously because the
// #296: ; frequency to be synthesized by the phase accumulator is 8 times smaller but the
// #297: ; value of 'S' is deliberate scaled to be as large as possible. In fact, 'S' in this
// #298: ; case has been scaled up by a factor of 8 to arrive at the same value. So after
// #299: ; using the scaling constant to form the 80 bit product, this time we will remove
// #300: ; the 46 LSBs and the 2 MSBs to leave the 32 active bits required. This is best
// #301: ; achieved by shifting left by 2 places (multiply by 2^2=4) and keeping the upper
// #302: ; 32-bits (last time we multiplied by 32 which was 8 times more).
// #303: ;
// #304: ;
// #305: ; Sanity check....
// #306: ;
// #307: ;     Ft = 100MHz =                         055FE100
// #308: ;               S =                  x  ABCC77118462
// #309: ;                               --------------------
// #310: ;                               04000000000001242200
// #311: ;
// #312: ;       shift left 5 places                     x 20
// #313: ;                               --------------------
// #314: ;                               1000000000001C908800
// #315: ;
// #316: ; As expected, the most significant 32-bit (4 bytes) are 10000000 hex which is
// #317: ; the DDS control word for 12.5MHz at the phase accumulator output calculated
// #318: ; previously.
// #319: ;
// #320: ;
// #321: ; ********
// #322: ;
// #323: ;
// #324: ; 48-bit Scaling factor constant to generate the phase accumulator control word
// #325: ; from the integer frequency value.
// #326: ;
// #327: ;   S = AB CC 77 11 84 62
// #328: ;
// #329: ; Notes
// #330: ;
// #331: ; The 80-bit product must be shifted left 5 times and then most significant 32-bits
// #332: ; used to provide DDS control word if the frequency required is to be synthesized
// #333: ; directly at the output of the phase accumulator.
// #334: ;
// #335: ; The 80-bit product must be shifted left 2 times and then most significant 32-bits
// #336: ; used to provide DDS control word if the frequency required is to be synthesized
// #337: ; by the phase accumulator followed by a multiplying DCM and divider with overall
// #338: ; frequency gain of 8 times.
// #339: ;
// #340: CONSTANT(scale_constant0,98) ;LS byte
// #341: CONSTANT(scale_constant1,132)
// #342: CONSTANT(scale_constant2,17)
// #343: CONSTANT(scale_constant3,119)
// #344: CONSTANT(scale_constant4,CC)
// #345: CONSTANT(scale_constant5,AB) ;MS byte
// #346: ;
// #347: ;
// #348: ;
// #349: ; ************************
// #350: ;
// #351: ;Constant to define a software delay of 1us. This must be adjusted to reflect the
// #352: ;clock applied to KCPSM3. Every instruction executes in 2 clock cycles making the