kcpsm2.v

和picoblaze完全兼容的mcu ip core

// It can also hold current value during an active interrupt
// and decrement by two during a RETURN or RETURNI.
//
// Counter 5 LUTs, 5 FDREs, and associated carry logic.
// Decoding lgic requires a futher 3 LUTs.
// Total size 4 slices.
//
//
module stack_counter (instruction17, instruction16, instruction14, instruction13, instruction12, T_state, flag_condition_met, active_interrupt, reset, stack_count, clk);

   input instruction17; 
   input instruction16; 
   input instruction14; 
   input instruction13; 
   input instruction12; 
   input T_state; 
   input flag_condition_met; 
   input active_interrupt; 
   input reset; 
   output[4:0] stack_count; 
   wire[4:0] stack_count;
   input clk; 

   wire not_interrupt; 
   wire[4:0] count_value; 
   wire[4:0] next_count; 
   wire[3:0] count_carry; 
   wire[4:0] half_count; 
   wire call_type; 
   wire valid_to_move; 
   wire push_or_pop_type; 

   INV invert_interrupt (.I(active_interrupt), .O(not_interrupt)); 

   LUT2 valid_move_lut(.I0(instruction12), .I1(flag_condition_met), .O(valid_to_move)); 
   // synthesis translate_off
   defparam valid_move_lut.INIT = 4'hD;
   // synthesis translate_on
   // synthesis attribute INIT of valid_move_lut "D"

   LUT4 call_lut(.I0(instruction13), .I1(instruction14), .I2(instruction16), .I3(instruction17), .O(call_type)); 
   // synthesis translate_off
   defparam call_lut.INIT = 16'h8000;
   // synthesis translate_on
   // synthesis attribute INIT of call_lut "8000"

   LUT4 push_pop_lut(.I0(instruction13), .I1(instruction14), .I2(instruction16), .I3(instruction17), .O(push_or_pop_type)); 
   // synthesis translate_off
   defparam push_pop_lut.INIT = 16'h8C00;
   // synthesis translate_on
   // synthesis attribute INIT of push_pop_lut "8C00"
   FDRE register_bit_0 (.D(next_count[0]), .Q(count_value[0]), .R(reset), .CE(not_interrupt), .C(clk));

   LUT4 count_lut_0(.I0(count_value[0]), .I1(T_state), .I2(valid_to_move), .I3(push_or_pop_type), .O(half_count[0])); 
   // synthesis translate_off
   defparam count_lut_0.INIT = 16'h6555;
   // synthesis translate_on
   // synthesis attribute INIT of count_lut_0 "6555"
   
   MUXCY count_muxcy_0 (.DI(count_value[0]), .CI(1'b0), .S(half_count[0]), .O(count_carry[0]));

   XORCY count_xor_0 (.LI(half_count[0]), .CI(1'b0), .O(next_count[0]));

   FDRE register_bit_1 (.D(next_count[1]), .Q(count_value[1]), .R(reset), .CE(not_interrupt), .C(clk));

   LUT4 count_lut_xhdl1_1(.I0(count_value[1]), .I1(T_state), .I2(valid_to_move), .I3(call_type), .O(half_count[1])); 
   // synthesis translate_off
   defparam count_lut_xhdl1_1.INIT = 16'hA999;
   // synthesis translate_on
   // synthesis attribute INIT of count_lut_xhdl1_1 "A999"
   MUXCY count_muxcy_xhdl2_1 (.DI(count_value[1]), .CI(count_carry[1 - 1]), .S(half_count[1]), .O(count_carry[1]));

   XORCY count_xor_xhdl3_1 (.LI(half_count[1]), .CI(count_carry[1 - 1]), .O(next_count[1]));

   FDRE register_bit_2 (.D(next_count[2]), .Q(count_value[2]), .R(reset), .CE(not_interrupt), .C(clk));

   LUT4 count_lut_xhdl1_2(.I0(count_value[2]), .I1(T_state), .I2(valid_to_move), .I3(call_type), .O(half_count[2])); 
   // synthesis translate_off
   defparam count_lut_xhdl1_2.INIT = 16'hA999;
   // synthesis translate_on
   // synthesis attribute INIT of count_lut_xhdl1_2 "A999"
   MUXCY count_muxcy_xhdl2_2 (.DI(count_value[2]), .CI(count_carry[2 - 1]), .S(half_count[2]), .O(count_carry[2]));

   XORCY count_xor_xhdl3_2 (.LI(half_count[2]), .CI(count_carry[2 - 1]), .O(next_count[2]));

   FDRE register_bit_3 (.D(next_count[3]), .Q(count_value[3]), .R(reset), .CE(not_interrupt), .C(clk));

   LUT4 count_lut_xhdl1_3(.I0(count_value[3]), .I1(T_state), .I2(valid_to_move), .I3(call_type), .O(half_count[3])); 
   // synthesis translate_off
   defparam count_lut_xhdl1_3.INIT = 16'hA999;
   // synthesis translate_on
   // synthesis attribute INIT of count_lut_xhdl1_3 "A999"
   MUXCY count_muxcy_xhdl2_3 (.DI(count_value[3]), .CI(count_carry[3 - 1]), .S(half_count[3]), .O(count_carry[3]));

   XORCY count_xor_xhdl3_3 (.LI(half_count[3]), .CI(count_carry[3 - 1]), .O(next_count[3]));

   FDRE register_bit_4 (.D(next_count[4]), .Q(count_value[4]), .R(reset), .CE(not_interrupt), .C(clk));

   LUT4 count_lut_xhdl4_4(.I0(count_value[4]), .I1(T_state), .I2(valid_to_move), .I3(call_type), .O(half_count[4])); 
   // synthesis translate_off
   defparam count_lut_xhdl4_4.INIT = 16'hA999;
   // synthesis translate_on
   // synthesis attribute INIT of count_lut_xhdl4_4 "A999"
   XORCY count_xor_xhdl5_4 (.LI(half_count[4]), .CI(count_carry[4 - 1]), .O(next_count[4])); 
   assign stack_count = count_value ;
endmodule

//----------------------------------------------------------------------------------
//
// Definition of RAM for stack
//	 
// This is a 32 location single port RAM of 10-bits to support the address range
// of the program counter. The ouput is registered and the write enable is active low.
//
// Ecah bit requires 1 slice, and therefore the 10-bit RAM requires 10-slices.
//
//
module stack_ram (Din, Dout, addr, write_bar, clk);

   input[9:0] Din; 
   output[9:0] Dout; 
   wire[9:0] Dout;
   input[4:0] addr; 
   input write_bar; 
   input clk; 

   wire[9:0] ram_out; 
   wire write_enable; 

   INV invert_enable (.I(write_bar), .O(write_enable)); 

   RAM32X1S stack_ram_bit_0(.D(Din[0]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[0])); 
   // synthesis translate_off
   defparam stack_ram_bit_0.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_0 "00000000"
   FD stack_ram_flop_0 (.D(ram_out[0]), .Q(Dout[0]), .C(clk));

   RAM32X1S stack_ram_bit_1(.D(Din[1]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[1])); 
   // synthesis translate_off
   defparam stack_ram_bit_1.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_1 "00000000"
   FD stack_ram_flop_1 (.D(ram_out[1]), .Q(Dout[1]), .C(clk));

   RAM32X1S stack_ram_bit_2(.D(Din[2]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[2])); 
   // synthesis translate_off
   defparam stack_ram_bit_2.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_2 "00000000"
   FD stack_ram_flop_2 (.D(ram_out[2]), .Q(Dout[2]), .C(clk));

   RAM32X1S stack_ram_bit_3(.D(Din[3]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[3])); 
   // synthesis translate_off
   defparam stack_ram_bit_3.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_3 "00000000"
   FD stack_ram_flop_3 (.D(ram_out[3]), .Q(Dout[3]), .C(clk));

   RAM32X1S stack_ram_bit_4(.D(Din[4]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[4])); 
   // synthesis translate_off
   defparam stack_ram_bit_4.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_4 "00000000"
   FD stack_ram_flop_4 (.D(ram_out[4]), .Q(Dout[4]), .C(clk));

   RAM32X1S stack_ram_bit_5(.D(Din[5]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[5])); 
   // synthesis translate_off
   defparam stack_ram_bit_5.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_5 "00000000"
   FD stack_ram_flop_5 (.D(ram_out[5]), .Q(Dout[5]), .C(clk));

   RAM32X1S stack_ram_bit_6(.D(Din[6]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[6])); 
   // synthesis translate_off
   defparam stack_ram_bit_6.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_6 "00000000"
   FD stack_ram_flop_6 (.D(ram_out[6]), .Q(Dout[6]), .C(clk));

   RAM32X1S stack_ram_bit_7(.D(Din[7]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[7])); 
   // synthesis translate_off
   defparam stack_ram_bit_7.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_7 "00000000"
   FD stack_ram_flop_7 (.D(ram_out[7]), .Q(Dout[7]), .C(clk));

   RAM32X1S stack_ram_bit_8(.D(Din[8]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[8])); 
   // synthesis translate_off
   defparam stack_ram_bit_8.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_8 "00000000"
   FD stack_ram_flop_8 (.D(ram_out[8]), .Q(Dout[8]), .C(clk));

   RAM32X1S stack_ram_bit_9(.D(Din[9]), .WE(write_enable), .WCLK(clk), .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .A4(addr[4]), .O(ram_out[9])); 
   // synthesis translate_off
   defparam stack_ram_bit_9.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of stack_ram_bit_9 "00000000"
   FD stack_ram_flop_9 (.D(ram_out[9]), .Q(Dout[9]), .C(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of basic time T-state and clean reset
//	
// This function forms the basic 2 cycle T-state control used by the processor.
// It also forms a clean synchronous reset pulse that is long enough to ensure 
// correct operation at start up and following a reset input.
// It uses 1 LUT, an FDR, and 2 FDS pimatives.
//
//
module T_state_and_Reset (reset_input, internal_reset, T_state, clk);

   input reset_input; 
   output internal_reset; 
   wire internal_reset;
   output T_state; 
   wire T_state;
   input clk; 

   wire reset_delay1; 
   wire reset_delay2; 
   wire not_T_state; 
   wire internal_T_state; 


   FDS delay_flop1 (.D(1'b0), .Q(reset_delay1), .S(reset_input), .C(clk)); 
   FDS delay_flop2 (.D(reset_delay1), .Q(reset_delay2), .S(reset_input), .C(clk)); 

   LUT1 invert_lut(.I0(internal_T_state), .O(not_T_state));
   // synthesis translate_off
   defparam invert_lut.INIT = 4'h1;
   // synthesis translate_on    
   // synthesis attribute INIT of invert_lut "1"
   FDR toggle_flop (.D(not_T_state), .Q(internal_T_state), .R(reset_delay2), .C(clk)); 
   assign T_state = internal_T_state ;
   assign internal_reset = reset_delay2 ;
endmodule

//----------------------------------------------------------------------------------
//
// Definition of the Zero Flag 
//	
// The ZERO value is detected using 2 LUTs and associated carry logic to 
// form a wired NOR gate. A further LUT selects the source for the ZERO flag
// which is stored in an FDRE.
//
//
module zero_flag_logic (data, instruction17, instruction14, shadow_zero, reset, flag_enable, zero_flag, clk);

   input[7:0] data; 
   input instruction17; 
   input instruction14; 
   input shadow_zero; 
   input reset; 
   input flag_enable; 
   output zero_flag; 
   wire zero_flag;
   input clk; 

   wire lower_zero; 
   wire upper_zero; 
   wire lower_zero_carry; 
   wire data_zero; 
   wire next_zero_flag; 

   LUT4 lower_zero_lut(.I0(data[0]), .I1(data[1]), .I2(data[2]), .I3(data[3]), .O(lower_zero)); 
   // synthesis translate_off
   defparam lower_zero_lut.INIT = 16'h0001;
   // synthesis translate_on
   // synthesis attribute INIT of lower_zero_lut "0001"

   LUT4 upper_zero_lut(.I0(data[4]), .I1(data[5]), .I2(data[6]), .I3(data[7]), .O(upper_zero)); 
   // synthesis translate_off
   defparam upper_zero_lut.INIT = 16'h0001;
   // synthesis translate_on
   // synthesis attribute INIT of upper_zero_lut "0001"

   MUXCY lower_carry (.DI(1'b0), .CI(1'b1), .S(lower_zero), .O(lower_zero_carry)); 
   MUXCY upper_carry (.DI(1'b0), .CI(lower_zero_carry), .S(upper_zero), .O(data_zero)); 

   LUT4 select_lut(.I0(instruction14), .I1(instruction17), .I2(data_zero), .I3(shadow_zero), .O(next_zero_flag)); 
   // s