kcpsm2.v

和picoblaze完全兼容的mcu ip core

   defparam logical_lut_2.INIT = 16'h6E8A;
   // synthesis translate_on
   // synthesis attribute INIT of logical_lut_2 "6E8A" 
   FD pipeline_bit_2 (.D(combinatorial_logical_processing[2]), .Q(Y[2]), .C(clk));

   LUT4 logical_lut_3(.I0(second_operand[3]), .I1(first_operand[3]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[3])); 
   // synthesis translate_off
   defparam logical_lut_3.INIT = 16'h6E8A;
   // synthesis translate_on
   // synthesis attribute INIT of logical_lut_3 "6E8A"
   FD pipeline_bit_3 (.D(combinatorial_logical_processing[3]), .Q(Y[3]), .C(clk));

   LUT4 logical_lut_4(.I0(second_operand[4]), .I1(first_operand[4]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[4])); 
   // synthesis translate_off
   defparam logical_lut_4.INIT = 16'h6E8A;
   // synthesis translate_on
   // synthesis attribute INIT of logical_lut_4 "6E8A"
   FD pipeline_bit_4 (.D(combinatorial_logical_processing[4]), .Q(Y[4]), .C(clk));

   LUT4 logical_lut_5(.I0(second_operand[5]), .I1(first_operand[5]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[5])); 
   // synthesis translate_off
   defparam logical_lut_5.INIT = 16'h6E8A;
   // synthesis translate_on
   // synthesis attribute INIT of logical_lut_5 "6E8A"
   FD pipeline_bit_5 (.D(combinatorial_logical_processing[5]), .Q(Y[5]), .C(clk));

   LUT4 logical_lut_6(.I0(second_operand[6]), .I1(first_operand[6]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[6])); 
   // synthesis translate_off
   defparam logical_lut_6.INIT = 16'h6E8A;
   // synthesis translate_on
   // synthesis attribute INIT of logical_lut_6 "6E8A"
   FD pipeline_bit_6 (.D(combinatorial_logical_processing[6]), .Q(Y[6]), .C(clk));

   LUT4 logical_lut_7(.I0(second_operand[7]), .I1(first_operand[7]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[7])); 
   // synthesis translate_off
   defparam logical_lut_7.INIT = 16'h6E8A;
   // synthesis translate_on
   // synthesis attribute INIT of logical_lut_7 "6E8A"
   FD pipeline_bit_7 (.D(combinatorial_logical_processing[7]), .Q(Y[7]), .C(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of a 2 to 1 multiplexer in a LUT
//
// This simple function is used many times.
//	 
//
module mux2_LUT (D1, D0, sel, Y);

   input D1; 
   input D0; 
   input sel; 
   output Y; 
   wire Y;
	
  LUT3 the_mux_lut(.I0(sel), .I1(D0), .I2(D1), .O(Y));
  // synthesis translate_off
  defparam the_mux_lut.INIT = 8'hE4;
  // synthesis translate_on   
  // synthesis attribute INIT of the_mux_lut "E4"
endmodule

//----------------------------------------------------------------------------------
//
// Definition of a 4 to 1 multiplexer using 2 LUTs and an MUXF5
//	 
// Builds on the definition of a 2 to 1 multiplexer on a LUT to 
// create a 4 to 1 multiplexer in a \'slice\'.
//
//
module mux4_LUTS_MUXF5 (D3, D2, D1, D0, sel1, sel0, Y);

   input D3; 
   input D2; 
   input D1; 
   input D0; 
   input sel1; 
   input sel0; 
   output Y; 
   wire Y;

   wire upper_selection; 
   wire lower_selection; 

   mux2_LUT upper_mux (.D1(D3), .D0(D2), .sel(sel0), .Y(upper_selection)); 
   mux2_LUT lower_mux (.D1(D1), .D0(D0), .sel(sel0), .Y(lower_selection)); 
   MUXF5 final_mux (.I1(upper_selection), .I0(lower_selection), .S(sel1), .O(Y)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 10-bit program counter
//	
// This function provides the control to the dual loadable counter macro which uses
// 3 LUTs. The total size of the program counter is then 23 LUTs (12 slices).
//
//
module program_counter (instruction17, instruction16, instruction15, instruction14, instruction12, low_instruction, stack_value, flag_condition_met, T_state, reset, force_3FF, program_count, clk);

   input instruction17; 
   input instruction16; 
   input instruction15; 
   input instruction14; 
   input instruction12; 
   input[9:0] low_instruction; 
   input[9:0] stack_value; 
   input flag_condition_met; 
   input T_state; 
   input reset; 
   input force_3FF; 
   output[9:0] program_count; 
   wire[9:0] program_count;
   input clk; 

   wire move_group; 
   wire normal_count; 
   wire increment_vector; 

   LUT4 move_group_lut(.I0(instruction14), .I1(instruction15), .I2(instruction16), .I3(instruction17), .O(move_group)); 
   // synthesis translate_off
   defparam move_group_lut.INIT = 16'h2A00;
   // synthesis translate_on
   // synthesis attribute INIT of move_group_lut "2A00"

   LUT3 normal_count_lut(.I0(instruction12), .I1(flag_condition_met), .I2(move_group), .O(normal_count)); 
   // synthesis translate_off
   defparam normal_count_lut.INIT = 8'h2F;
   // synthesis translate_on
   // synthesis attribute INIT of normal_count_lut "2F"

   LUT2 inc_vector_lut(.I0(instruction15), .I1(instruction16), .O(increment_vector)); 
   // synthesis translate_off
   defparam inc_vector_lut.INIT = 4'h1;
   // synthesis translate_on
   // synthesis attribute INIT of inc_vector_lut "1"
   dual_loadable_counter the_counter (.load_1_value(low_instruction), .load_0_value(stack_value), .select_load_value(instruction16), .increment_load_value(increment_vector), .normal_count(normal_count), .enable_bar(T_state), .reset(reset), .force_3FF(force_3FF), .count(program_count), .clk(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of write enable for register bank and flags
//	
// This function decodes all instructions which result in a value being stored
// in the data registers and those cases in which the flags must be enabled. 
// It uses 5 LUTs and and 3 FDs.
// The generation of a register enable pulse is prevented by an active interrupt condition.
// The single cycle pulse timing of each enable is determined by the T-state.  
//
//
module register_and_flag_enable (instruction, active_interrupt, T_state, register_enable, flag_enable, clk);

   input[17:13] instruction; 
   input active_interrupt; 
   input T_state; 
   output register_enable; 
   wire register_enable;
   output flag_enable; 
   wire flag_enable;
   input clk; 

   wire reg_instruction_decode; 
   wire register_write_valid; 
   wire returni_or_shift_decode; 
   wire returni_or_shift_valid; 
   wire arith_or_logical_decode; 
   wire arith_or_logical_valid; 

   LUT4 reg_decode_lut(.I0(active_interrupt), .I1(instruction[13]), .I2(instruction[14]), .I3(instruction[17]), .O(reg_instruction_decode)); 
   // synthesis translate_off
   defparam reg_decode_lut.INIT = 16'h0155;
   // synthesis translate_on
   // synthesis attribute INIT of reg_decode_lut "0155"
   FD reg_pipeline_bit (.D(reg_instruction_decode), .Q(register_write_valid), .C(clk)); 

   LUT2 reg_pulse_timing_lut(.I0(T_state), .I1(register_write_valid), .O(register_enable)); 
   // synthesis translate_off
   defparam reg_pulse_timing_lut.INIT = 4'h8;
   // synthesis translate_on
   // synthesis attribute INIT of reg_pulse_timing_lut "8"

   LUT4 flag_decode1_lut(.I0(instruction[13]), .I1(instruction[14]), .I2(instruction[15]), .I3(instruction[17]), .O(arith_or_logical_decode)); 
   // synthesis translate_off
   defparam flag_decode1_lut.INIT = 16'h00FE;
   // synthesis translate_on
   // synthesis attribute INIT of flag_decode1_lut "00FE" 
   FD flag_pipeline1_bit (.D(arith_or_logical_decode), .Q(arith_or_logical_valid), .C(clk)); 

   LUT3 flag_decode2_lut(.I0(instruction[15]), .I1(instruction[16]), .I2(instruction[17]), .O(returni_or_shift_decode)); 
   // synthesis translate_off
   defparam flag_decode2_lut.INIT = 8'h20;
   // synthesis translate_on
   // synthesis attribute INIT of flag_decode2_lut "20"
   FD flag_pipeline2_bit (.D(returni_or_shift_decode), .Q(returni_or_shift_valid), .C(clk)); 

   LUT3 flag_pulse_timing_lut(.I0(T_state), .I1(arith_or_logical_valid), .I2(returni_or_shift_valid), .O(flag_enable)); 
   // synthesis translate_off
   defparam flag_pulse_timing_lut.INIT = 8'hA8;
   // synthesis translate_on
   // synthesis attribute INIT of flag_pulse_timing_lut "A8"
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 8-bit shift/rotate process
//	
// This function uses 11 LUTs.
// The function contains an output pipeline register using 9 FDs.
//
// Operation
//
// The input operand is shifted by one bit left or right.
// The bit which falls out of the end is passed to the carry_out.
// The bit shifted in is determined by the select bits
//
//     code1    code0         Bit injected
//
//       0        0          carry_in           
//       0        1          msb of input_operand 
//       1        0          lsb of operand 
//       1        1          inject_bit 
//
//
module shift_rotate_process (operand, carry_in, inject_bit, shift_right, code1, code0, Y, carry_out, clk);

   input[7:0] operand; 
   input carry_in; 
   input inject_bit; 
   input shift_right; 
   input code1; 
   input code0; 
   output[7:0] Y; 
   wire[7:0] Y;
   output carry_out; 
   wire carry_out;
   input clk; 

   wire[7:0] mux_output; 
   wire shift_in_bit; 
   wire carry_bit; 

   mux4_LUTS_MUXF5 input_bit_mux4 (.D3(inject_bit), .D2(operand[0]), .D1(operand[7]), .D0(carry_in), .sel1(code1), .sel0(code0), .Y(shift_in_bit)); 
   mux2_LUT bit_mux2_0 (.D1(operand[0 + 1]), .D0(shift_in_bit), .sel(shift_right), .Y(mux_output[0]));

   FD pipeline_bit_0 (.D(mux_output[0]), .Q(Y[0]), .C(clk));

   mux2_LUT bit_mux2_xhdl1_1 (.D1(operand[1 + 1]), .D0(operand[1 - 1]), .sel(shift_right), .Y(mux_output[1]));

   FD pipeline_bit_1 (.D(mux_output[1]), .Q(Y[1]), .C(clk));

   mux2_LUT bit_mux2_xhdl1_2 (.D1(operand[2 + 1]), .D0(operand[2 - 1]), .sel(shift_right), .Y(mux_output[2]));

   FD pipeline_bit_2 (.D(mux_output[2]), .Q(Y[2]), .C(clk));

   mux2_LUT bit_mux2_xhdl1_3 (.D1(operand[3 + 1]), .D0(operand[3 - 1]), .sel(shift_right), .Y(mux_output[3]));

   FD pipeline_bit_3 (.D(mux_output[3]), .Q(Y[3]), .C(clk));

   mux2_LUT bit_mux2_xhdl1_4 (.D1(operand[4 + 1]), .D0(operand[4 - 1]), .sel(shift_right), .Y(mux_output[4]));

   FD pipeline_bit_4 (.D(mux_output[4]), .Q(Y[4]), .C(clk));

   mux2_LUT bit_mux2_xhdl1_5 (.D1(operand[5 + 1]), .D0(operand[5 - 1]), .sel(shift_right), .Y(mux_output[5]));

   FD pipeline_bit_5 (.D(mux_output[5]), .Q(Y[5]), .C(clk));

   mux2_LUT bit_mux2_xhdl1_6 (.D1(operand[6 + 1]), .D0(operand[6 - 1]), .sel(shift_right), .Y(mux_output[6]));

   FD pipeline_bit_6 (.D(mux_output[6]), .Q(Y[6]), .C(clk));

   mux2_LUT bit_mux2_xhdl2_7 (.D1(shift_in_bit), .D0(operand[7 - 1]), .sel(shift_right), .Y(mux_output[7]));

   FD pipeline_bit_7 (.D(mux_output[7]), .Q(Y[7]), .C(clk)); 
   mux2_LUT carry_out_mux2 (.D1(operand[0]), .D0(operand[7]), .sel(shift_right), .Y(carry_bit)); 
   FD pipeline_bit_xhdl3 (.D(carry_bit), .Q(carry_out), .C(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of a 5-bit special counter for stack pointer
//	
// This 5-bit counter is a relatively complex function
//
// The counter is able to increment and decrement.