kcpsm2.v

和picoblaze完全兼容的mcu ip core

   FDRSE register_bit_4 (.D(inc_count_value[4]), .Q(count_value[4]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_4 (.DI(1'b0), .CI(inc_load_value_carry[4 - 1]), .S(selected_load_value[4]), .O(inc_load_value_carry[4]));

   XORCY load_inc_xor_xhdl2_4 (.LI(selected_load_value[4]), .CI(inc_load_value_carry[4 - 1]), .O(inc_load_value[4]));

   MUXCY count_inc_carry_xhdl3_4 (.DI(1'b0), .CI(inc_count_value_carry[4 - 1]), .S(selected_count_value[4]), .O(inc_count_value_carry[4]));

   XORCY count_inc_xor_xhdl4_4 (.LI(selected_count_value[4]), .CI(inc_count_value_carry[4 - 1]), .O(inc_count_value[4]));

   mux2_LUT value_select_mux_5 (.D1(load_1_value[5]), .D0(load_0_value[5]), .sel(select_load_value), .Y(selected_load_value[5]));

   mux2_LUT count_select_mux_5 (.D1(count_value[5]), .D0(inc_load_value[5]), .sel(normal_count), .Y(selected_count_value[5]));

   FDRSE register_bit_5 (.D(inc_count_value[5]), .Q(count_value[5]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_5 (.DI(1'b0), .CI(inc_load_value_carry[5 - 1]), .S(selected_load_value[5]), .O(inc_load_value_carry[5]));

   XORCY load_inc_xor_xhdl2_5 (.LI(selected_load_value[5]), .CI(inc_load_value_carry[5 - 1]), .O(inc_load_value[5]));

   MUXCY count_inc_carry_xhdl3_5 (.DI(1'b0), .CI(inc_count_value_carry[5 - 1]), .S(selected_count_value[5]), .O(inc_count_value_carry[5]));

   XORCY count_inc_xor_xhdl4_5 (.LI(selected_count_value[5]), .CI(inc_count_value_carry[5 - 1]), .O(inc_count_value[5]));

   mux2_LUT value_select_mux_6 (.D1(load_1_value[6]), .D0(load_0_value[6]), .sel(select_load_value), .Y(selected_load_value[6]));

   mux2_LUT count_select_mux_6 (.D1(count_value[6]), .D0(inc_load_value[6]), .sel(normal_count), .Y(selected_count_value[6]));

   FDRSE register_bit_6 (.D(inc_count_value[6]), .Q(count_value[6]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_6 (.DI(1'b0), .CI(inc_load_value_carry[6 - 1]), .S(selected_load_value[6]), .O(inc_load_value_carry[6]));

   XORCY load_inc_xor_xhdl2_6 (.LI(selected_load_value[6]), .CI(inc_load_value_carry[6 - 1]), .O(inc_load_value[6]));

   MUXCY count_inc_carry_xhdl3_6 (.DI(1'b0), .CI(inc_count_value_carry[6 - 1]), .S(selected_count_value[6]), .O(inc_count_value_carry[6]));

   XORCY count_inc_xor_xhdl4_6 (.LI(selected_count_value[6]), .CI(inc_count_value_carry[6 - 1]), .O(inc_count_value[6]));

   mux2_LUT value_select_mux_7 (.D1(load_1_value[7]), .D0(load_0_value[7]), .sel(select_load_value), .Y(selected_load_value[7]));

   mux2_LUT count_select_mux_7 (.D1(count_value[7]), .D0(inc_load_value[7]), .sel(normal_count), .Y(selected_count_value[7]));

   FDRSE register_bit_7 (.D(inc_count_value[7]), .Q(count_value[7]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_7 (.DI(1'b0), .CI(inc_load_value_carry[7 - 1]), .S(selected_load_value[7]), .O(inc_load_value_carry[7]));

   XORCY load_inc_xor_xhdl2_7 (.LI(selected_load_value[7]), .CI(inc_load_value_carry[7 - 1]), .O(inc_load_value[7]));

   MUXCY count_inc_carry_xhdl3_7 (.DI(1'b0), .CI(inc_count_value_carry[7 - 1]), .S(selected_count_value[7]), .O(inc_count_value_carry[7]));

   XORCY count_inc_xor_xhdl4_7 (.LI(selected_count_value[7]), .CI(inc_count_value_carry[7 - 1]), .O(inc_count_value[7]));

   mux2_LUT value_select_mux_8 (.D1(load_1_value[8]), .D0(load_0_value[8]), .sel(select_load_value), .Y(selected_load_value[8]));

   mux2_LUT count_select_mux_8 (.D1(count_value[8]), .D0(inc_load_value[8]), .sel(normal_count), .Y(selected_count_value[8]));

   FDRSE register_bit_8 (.D(inc_count_value[8]), .Q(count_value[8]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_8 (.DI(1'b0), .CI(inc_load_value_carry[8 - 1]), .S(selected_load_value[8]), .O(inc_load_value_carry[8]));

   XORCY load_inc_xor_xhdl2_8 (.LI(selected_load_value[8]), .CI(inc_load_value_carry[8 - 1]), .O(inc_load_value[8]));

   MUXCY count_inc_carry_xhdl3_8 (.DI(1'b0), .CI(inc_count_value_carry[8 - 1]), .S(selected_count_value[8]), .O(inc_count_value_carry[8]));

   XORCY count_inc_xor_xhdl4_8 (.LI(selected_count_value[8]), .CI(inc_count_value_carry[8 - 1]), .O(inc_count_value[8]));

   mux2_LUT value_select_mux_9 (.D1(load_1_value[9]), .D0(load_0_value[9]), .sel(select_load_value), .Y(selected_load_value[9]));

   mux2_LUT count_select_mux_9 (.D1(count_value[9]), .D0(inc_load_value[9]), .sel(normal_count), .Y(selected_count_value[9]));

   FDRSE register_bit_9 (.D(inc_count_value[9]), .Q(count_value[9]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   XORCY load_inc_xor_xhdl5_9 (.LI(selected_load_value[9]), .CI(inc_load_value_carry[9 - 1]), .O(inc_load_value[9]));

   XORCY count_inc_xor_xhdl6_9 (.LI(selected_count_value[9]), .CI(inc_count_value_carry[9 - 1]), .O(inc_count_value[9])); 
   assign count = count_value ;
endmodule

//----------------------------------------------------------------------------------
//
// Decode of flag conditions 
//	
// This function determines if the flags meet the conditions specified in a 
// JUMP, CALL, or RETURN instruction. It is defined as a separate macro because 
// it provides information required by both the program counter and stack pointer.
//
// It uses 1 LUT.
//
//
module flag_test (instruction11, instruction10, zero_flag, carry_flag, condition_met);

   input instruction11; 
   input instruction10; 
   input zero_flag; 
   input carry_flag; 
   output condition_met; 
   wire condition_met;

   LUT4 decode_lut(.I0(carry_flag), .I1(zero_flag), .I2(instruction10), .I3(instruction11), .O(condition_met)); 
   // synthesis translate_off
   defparam decode_lut.INIT = 16'h5A3C;
   // synthesis translate_on
   // synthesis attribute INIT of decode_lut "5A3C"
endmodule

//----------------------------------------------------------------------------------
//
// Definition of interrupt signal capture
//	
// This function accepts the external interrupt signal and synchronises it to the 
// processor logic. It then forms a single cycle pulse provided that interrupts 
// are currently enabled.
//
// It uses 1 LUT and 2 FDs.
//
//
module interrupt_capture (interrupt, T_state, reset, interrupt_enable, active_interrupt, clk);

   input interrupt; 
   input T_state; 
   input reset; 
   input interrupt_enable; 
   output active_interrupt; 
   wire active_interrupt;
   input clk; 

   wire clean_interrupt; 
   wire interrupt_pulse; 
   wire active_interrupt_pulse; 

   FDR input_flop (.D(interrupt), .Q(clean_interrupt), .R(reset), .C(clk)); 

   LUT4 interrupt_pulse_lut(.I0(T_state), .I1(clean_interrupt), .I2(interrupt_enable), .I3(active_interrupt_pulse), .O(interrupt_pulse)); 
   // synthesis translate_off
   defparam interrupt_pulse_lut.INIT = 16'h0080;
   // synthesis translate_on
   // synthesis attribute INIT of interrupt_pulse_lut "0080"
   FDR toggle_flop (.D(interrupt_pulse), .Q(active_interrupt_pulse), .R(reset), .C(clk)); 
   assign active_interrupt = active_interrupt_pulse ;
endmodule

//----------------------------------------------------------------------------------
//
// Definition of interrupt enable and shaddow flags
//	
// This function decodes the ENABLE and DSIABLE INTERRUPT instructions as well as
// the RETURNI ENABLE and RETURNI DISABLE instructions to determine if future interrupts
// will be enabled.
//
// It also provideds the shaddow flags which store the flag status at time of an 
// interrupt.
//
// It uses 2 LUTs and 3 FDs.
//
//
module interrupt_logic (instruction17, instruction15, instruction14, instruction0, active_interrupt, carry_flag, zero_flag, reset, interrupt_enable, shaddow_carry, shaddow_zero, clk);

   input instruction17; 
   input instruction15; 
   input instruction14; 
   input instruction0; 
   input active_interrupt; 
   input carry_flag; 
   input zero_flag; 
   input reset; 
   output interrupt_enable; 
   wire interrupt_enable;
   output shaddow_carry; 
   wire shaddow_carry;
   output shaddow_zero; 
   wire shaddow_zero;
   input clk; 

   wire update_enable; 
   wire new_enable_value; 

   LUT4 decode_lut(.I0(active_interrupt), .I1(instruction14), .I2(instruction15), .I3(instruction17), .O(update_enable)); 
   // synthesis translate_off
   defparam decode_lut.INIT = 16'hEAAA;
   // synthesis translate_on
   // synthesis attribute INIT of decode_lut "EAAA"

   LUT2 value_lut(.I0(active_interrupt), .I1(instruction0), .O(new_enable_value)); 
   // synthesis translate_off
   defparam value_lut.INIT = 4'h4;
   // synthesis translate_on
   // synthesis attribute INIT of value_lut "4"
   FDRE int_enable_flop (.D(new_enable_value), .Q(interrupt_enable), .CE(update_enable), .R(reset), .C(clk)); 
   FDE preserve_carry_flop (.D(carry_flag), .Q(shaddow_carry), .CE(active_interrupt), .C(clk)); 
   FDE preserve_zero_flop (.D(zero_flag), .Q(shaddow_zero), .CE(active_interrupt), .C(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of the Input and Output Strobes 
//	
// Uses 3 LUTs and 2 FDR.
//
//
module IO_strobe_logic (instruction17, instruction15, instruction14, instruction13, active_interrupt, T_state, reset, write_strobe, read_strobe, clk);

   input instruction17; 
   input instruction15; 
   input instruction14; 
   input instruction13; 
   input active_interrupt; 
   input T_state; 
   input reset; 
   output write_strobe; 
   wire write_strobe;
   output read_strobe; 
   wire read_strobe;
   input clk; 

   wire IO_type; 
   wire write_event; 
   wire read_event; 
   
   LUT3 IO_type_lut(.I0(instruction14), .I1(instruction15), .I2(instruction17), .O(IO_type)); 
   // synthesis translate_off
   defparam IO_type_lut.INIT = 8'h10;
   // synthesis translate_on
   // synthesis attribute INIT of IO_type_lut "10"

   LUT4 write_lut(.I0(active_interrupt), .I1(T_state), .I2(instruction13), .I3(IO_type), .O(write_event)); 
   // synthesis translate_off
   defparam write_lut.INIT = 16'h1000;
   // synthesis translate_on
   // synthesis attribute INIT of write_lut "1000"
   FDR write_flop (.D(write_event), .Q(write_strobe), .R(reset), .C(clk)); 

   LUT4 read_lut(.I0(active_interrupt), .I1(T_state), .I2(instruction13), .I3(IO_type), .O(read_event)); 
   // synthesis translate_off
   defparam read_lut.INIT = 16'h0100;
   // synthesis translate_on
   // synthesis attribute INIT of read_lut "0100"
   FDR read_flop (.D(read_event), .Q(read_strobe), .R(reset), .C(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 8-bit logical processing unit
//	
// This function uses 8 LUTs (4 slices) to provide the logical bit operations.
// The function contains an output pipeline register using 8 FDs.
//
//     Code1    Code0       Bit Operation
//
//       0        0            LOAD      Y <= second_operand 
//       0        1            AND       Y <= first_operand and second_operand
//       1        0            OR        Y <= first_operand or second_operand 
//       1        1            XOR       Y <= first_operand xor second_operand
//
//
module logical_bus_processing (first_operand, second_operand, code1, code0, Y, clk);

   input[7:0] first_operand; 
   input[7:0] second_operand; 
   input code1; 
   input code0; 
   output[7:0] Y; 
   wire[7:0] Y;
   input clk; 

   wire[7:0] combinatorial_logical_processing; 

   LUT4 logical_lut_0(.I0(second_operand[0]), .I1(first_operand[0]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[0])); 
   // synthesis translate_off
   defparam logical_lut_0.INIT = 16'h6E8A;
   // synthesis translate_on
   // synthesis attribute INIT of logical_lut_0 "6E8A"

   FD pipeline_bit_0 (.D(combinatorial_logical_processing[0]), .Q(Y[0]), .C(clk));

   LUT4 logical_lut_1(.I0(second_operand[1]), .I1(first_operand[1]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[1])); 
   // synthesis translate_off
   defparam logical_lut_1.INIT = 16'h6E8A;
   // synthesis translate_on 
   // synthesis attribute INIT of logical_lut_1 "6E8A"
   FD pipeline_bit_1 (.D(combinatorial_logical_processing[1]), .Q(Y[1]), .C(clk));

   LUT4 logical_lut_2(.I0(second_operand[2]), .I1(first_operand[2]), .I2(code0), .I3(code1), .O(combinatorial_logical_processing[2])); 
   // synthesis translate_off