kcpsm2.v

和picoblaze完全兼容的mcu ip core

endmodule

//----------------------------------------------------------------------------------
//
// Definition of the Carry Flag 
//
// 2 LUTs are used to select the source for the CARRY flag
// which is stored in an FDRE.
//	
//
module carry_flag_logic (instruction17, instruction15, instruction14, shift_carry, add_sub_carry, shadow_carry, reset, flag_enable, carry_flag, clk);

   input instruction17; 
   input instruction15; 
   input instruction14; 
   input shift_carry; 
   input add_sub_carry; 
   input shadow_carry; 
   input reset; 
   input flag_enable; 
   output carry_flag; 
   wire carry_flag;
   input clk; 

   wire carry_status; 
   wire next_carry_flag; 

   LUT4 status_lut(.I0(instruction15), .I1(instruction17), .I2(add_sub_carry), .I3(shift_carry), .O(carry_status)); 
   // synthesis translate_off
   defparam status_lut.INIT = 16'hEC20;
   // synthesis translate_on
   // synthesis attribute INIT of status_lut "EC20"

   LUT4 select_lut(.I0(instruction14), .I1(instruction17), .I2(carry_status), .I3(shadow_carry), .O(next_carry_flag)); 
   // synthesis translate_off
   defparam select_lut.INIT = 16'hF870;
   // synthesis translate_on
   // synthesis attribute INIT of select_lut "F870"
   FDRE carry_flag_flop (.D(next_carry_flag), .Q(carry_flag), .CE(flag_enable), .R(reset), .C(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 8-bit bus 2 to 1 multiplexer
//
// Requires 8 LUTs or 4 \'slices\'.
//	 
//
module data_bus_mux2 (D1_bus, D0_bus, sel, Y_bus);

   input[7:0] D1_bus; 
   input[7:0] D0_bus; 
   input sel; 
   output[7:0] Y_bus; 
   wire[7:0] Y_bus;

   mux2_LUT bit_mux2_0 (.D1(D1_bus[0]), .D0(D0_bus[0]), .sel(sel), .Y(Y_bus[0]));

   mux2_LUT bit_mux2_1 (.D1(D1_bus[1]), .D0(D0_bus[1]), .sel(sel), .Y(Y_bus[1]));

   mux2_LUT bit_mux2_2 (.D1(D1_bus[2]), .D0(D0_bus[2]), .sel(sel), .Y(Y_bus[2]));

   mux2_LUT bit_mux2_3 (.D1(D1_bus[3]), .D0(D0_bus[3]), .sel(sel), .Y(Y_bus[3]));

   mux2_LUT bit_mux2_4 (.D1(D1_bus[4]), .D0(D0_bus[4]), .sel(sel), .Y(Y_bus[4]));

   mux2_LUT bit_mux2_5 (.D1(D1_bus[5]), .D0(D0_bus[5]), .sel(sel), .Y(Y_bus[5]));

   mux2_LUT bit_mux2_6 (.D1(D1_bus[6]), .D0(D0_bus[6]), .sel(sel), .Y(Y_bus[6]));

   mux2_LUT bit_mux2_7 (.D1(D1_bus[7]), .D0(D0_bus[7]), .sel(sel), .Y(Y_bus[7])); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 8-bit bus 4 to 1 multiplexer
//	 
// Requires 8 \'slices\'.
//
//
module data_bus_mux4 (D3_bus, D2_bus, D1_bus, D0_bus, sel1, sel0, Y_bus);

   input[7:0] D3_bus; 
   input[7:0] D2_bus; 
   input[7:0] D1_bus; 
   input[7:0] D0_bus; 
   input sel1; 
   input sel0; 
   output[7:0] Y_bus; 
   wire[7:0] Y_bus;

   mux4_LUTS_MUXF5 bit_mux4_0 (.D3(D3_bus[0]), .D2(D2_bus[0]), .D1(D1_bus[0]), .D0(D0_bus[0]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[0]));

   mux4_LUTS_MUXF5 bit_mux4_1 (.D3(D3_bus[1]), .D2(D2_bus[1]), .D1(D1_bus[1]), .D0(D0_bus[1]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[1]));

   mux4_LUTS_MUXF5 bit_mux4_2 (.D3(D3_bus[2]), .D2(D2_bus[2]), .D1(D1_bus[2]), .D0(D0_bus[2]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[2]));

   mux4_LUTS_MUXF5 bit_mux4_3 (.D3(D3_bus[3]), .D2(D2_bus[3]), .D1(D1_bus[3]), .D0(D0_bus[3]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[3]));

   mux4_LUTS_MUXF5 bit_mux4_4 (.D3(D3_bus[4]), .D2(D2_bus[4]), .D1(D1_bus[4]), .D0(D0_bus[4]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[4]));

   mux4_LUTS_MUXF5 bit_mux4_5 (.D3(D3_bus[5]), .D2(D2_bus[5]), .D1(D1_bus[5]), .D0(D0_bus[5]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[5]));

   mux4_LUTS_MUXF5 bit_mux4_6 (.D3(D3_bus[6]), .D2(D2_bus[6]), .D1(D1_bus[6]), .D0(D0_bus[6]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[6]));

   mux4_LUTS_MUXF5 bit_mux4_7 (.D3(D3_bus[7]), .D2(D2_bus[7]), .D1(D1_bus[7]), .D0(D0_bus[7]), .sel1(sel1), .sel0(sel0), .Y(Y_bus[7])); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 8-bit dual port RAM with 32 locations
//	
// This mode of distributed RAM requires 2 \'slices\' per bit.
// Hence this 8-bit module requires 16 \'slices\'.
// 
//
module data_register_bank (Address_A, Din_A_bus, Write_A_bus, Dout_A_bus, Address_B, Dout_B_bus, clk);

   input[4:0] Address_A; 
   input[7:0] Din_A_bus; 
   input Write_A_bus; 
   output[7:0] Dout_A_bus; 
   wire[7:0] Dout_A_bus;
   input[4:0] Address_B; 
   output[7:0] Dout_B_bus; 
   wire[7:0] Dout_B_bus;
   input clk; 

   RAM32X1D data_register_bit_0(.D(Din_A_bus[0]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[0]), .DPO(Dout_B_bus[0])); 
   // synthesis translate_off
   defparam data_register_bit_0.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_0 "00000000"

   RAM32X1D data_register_bit_1(.D(Din_A_bus[1]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[1]), .DPO(Dout_B_bus[1])); 
   // synthesis translate_off
   defparam data_register_bit_1.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_1 "00000000"

   RAM32X1D data_register_bit_2(.D(Din_A_bus[2]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[2]), .DPO(Dout_B_bus[2])); 
   // synthesis translate_off
   defparam data_register_bit_2.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_2 "00000000"

   RAM32X1D data_register_bit_3(.D(Din_A_bus[3]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[3]), .DPO(Dout_B_bus[3])); 
   // synthesis translate_off
   defparam data_register_bit_3.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_3 "00000000"

   RAM32X1D data_register_bit_4(.D(Din_A_bus[4]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[4]), .DPO(Dout_B_bus[4])); 
   // synthesis translate_off
   defparam data_register_bit_4.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_4 "00000000"

   RAM32X1D data_register_bit_5(.D(Din_A_bus[5]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[5]), .DPO(Dout_B_bus[5])); 
   // synthesis translate_off
   defparam data_register_bit_5.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_5 "00000000"

   RAM32X1D data_register_bit_6(.D(Din_A_bus[6]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[6]), .DPO(Dout_B_bus[6])); 
   // synthesis translate_off
   defparam data_register_bit_6.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_6 "00000000"

   RAM32X1D data_register_bit_7(.D(Din_A_bus[7]), .WE(Write_A_bus), .WCLK(clk), .A0(Address_A[0]), .A1(Address_A[1]), .A2(Address_A[2]), .A3(Address_A[3]), .A4(Address_A[4]), .DPRA0(Address_B[0]), .DPRA1(Address_B[1]), .DPRA2(Address_B[2]), .DPRA3(Address_B[3]), .DPRA4(Address_B[4]), .SPO(Dout_A_bus[7]), .DPO(Dout_B_bus[7]));  
   // synthesis translate_off
   defparam data_register_bit_7.INIT = 32'h00000000;
   // synthesis translate_on
   // synthesis attribute INIT of data_register_bit_7 "00000000"
endmodule

//----------------------------------------------------------------------------------
//
// Definition of a 10-bit dual loadable counter for use as Program Counter
//	
// This function uses 20 LUTs and associated MUXCY/XORCY components.
// The count value is held in 10 FDs.
//
// Operation
//
// When the normal_count signal is high the 10-bit counter will simply increment
// by selecting the feedback from the register and incrementing it.
//
// When the normal_count signal is low, the counter will load a new input value.
// The new value can be selected from one of two inputs, and optionally incremented
// before being applied to the counter register. 
//
// In this way the counter can load an absolute value used during a JUMP or CALL,
// instruction, or alternatively, load a value from the stack during a RETURN or 
// RETURNI instruction. During a RETURN, the value must be incremented.
//
// The register has an active low clock enable and a reset. 
// It also has the ability to be forced to maximum count (3FF) in the event of an interrupt.
//
//
module dual_loadable_counter (load_1_value, load_0_value, select_load_value, increment_load_value, normal_count, enable_bar, reset, force_3FF, count, clk);

   input[9:0] load_1_value; 
   input[9:0] load_0_value; 
   input select_load_value; 
   input increment_load_value; 
   input normal_count; 
   input enable_bar; 
   input reset; 
   input force_3FF; 
   output[9:0] count; 
   wire[9:0] count;
   input clk; 

   wire not_enable; 
   wire[9:0] selected_load_value; 
   wire[8:0] inc_load_value_carry; 
   wire[9:0] inc_load_value; 
   wire[9:0] selected_count_value; 
   wire[8:0] inc_count_value_carry; 
   wire[9:0] inc_count_value; 
   wire[9:0] count_value; 

   INV invert_enable (.I(enable_bar), .O(not_enable)); 
   mux2_LUT value_select_mux_0 (.D1(load_1_value[0]), .D0(load_0_value[0]), .sel(select_load_value), .Y(selected_load_value[0]));

   mux2_LUT count_select_mux_0 (.D1(count_value[0]), .D0(inc_load_value[0]), .sel(normal_count), .Y(selected_count_value[0]));

   FDRSE register_bit_0 (.D(inc_count_value[0]), .Q(count_value[0]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_0 (.DI(1'b0), .CI(increment_load_value), .S(selected_load_value[0]), .O(inc_load_value_carry[0]));

   XORCY load_inc_xor_0 (.LI(selected_load_value[0]), .CI(increment_load_value), .O(inc_load_value[0]));

   MUXCY count_inc_carry_0 (.DI(1'b0), .CI(normal_count), .S(selected_count_value[0]), .O(inc_count_value_carry[0]));

   XORCY count_inc_xor_0 (.LI(selected_count_value[0]), .CI(normal_count), .O(inc_count_value[0]));

   mux2_LUT value_select_mux_1 (.D1(load_1_value[1]), .D0(load_0_value[1]), .sel(select_load_value), .Y(selected_load_value[1]));

   mux2_LUT count_select_mux_1 (.D1(count_value[1]), .D0(inc_load_value[1]), .sel(normal_count), .Y(selected_count_value[1]));

   FDRSE register_bit_1 (.D(inc_count_value[1]), .Q(count_value[1]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_1 (.DI(1'b0), .CI(inc_load_value_carry[1 - 1]), .S(selected_load_value[1]), .O(inc_load_value_carry[1]));

   XORCY load_inc_xor_xhdl2_1 (.LI(selected_load_value[1]), .CI(inc_load_value_carry[1 - 1]), .O(inc_load_value[1]));

   MUXCY count_inc_carry_xhdl3_1 (.DI(1'b0), .CI(inc_count_value_carry[1 - 1]), .S(selected_count_value[1]), .O(inc_count_value_carry[1]));

   XORCY count_inc_xor_xhdl4_1 (.LI(selected_count_value[1]), .CI(inc_count_value_carry[1 - 1]), .O(inc_count_value[1]));

   mux2_LUT value_select_mux_2 (.D1(load_1_value[2]), .D0(load_0_value[2]), .sel(select_load_value), .Y(selected_load_value[2]));

   mux2_LUT count_select_mux_2 (.D1(count_value[2]), .D0(inc_load_value[2]), .sel(normal_count), .Y(selected_count_value[2]));

   FDRSE register_bit_2 (.D(inc_count_value[2]), .Q(count_value[2]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_2 (.DI(1'b0), .CI(inc_load_value_carry[2 - 1]), .S(selected_load_value[2]), .O(inc_load_value_carry[2]));

   XORCY load_inc_xor_xhdl2_2 (.LI(selected_load_value[2]), .CI(inc_load_value_carry[2 - 1]), .O(inc_load_value[2]));

   MUXCY count_inc_carry_xhdl3_2 (.DI(1'b0), .CI(inc_count_value_carry[2 - 1]), .S(selected_count_value[2]), .O(inc_count_value_carry[2]));

   XORCY count_inc_xor_xhdl4_2 (.LI(selected_count_value[2]), .CI(inc_count_value_carry[2 - 1]), .O(inc_count_value[2]));

   mux2_LUT value_select_mux_3 (.D1(load_1_value[3]), .D0(load_0_value[3]), .sel(select_load_value), .Y(selected_load_value[3]));

   mux2_LUT count_select_mux_3 (.D1(count_value[3]), .D0(inc_load_value[3]), .sel(normal_count), .Y(selected_count_value[3]));

   FDRSE register_bit_3 (.D(inc_count_value[3]), .Q(count_value[3]), .R(reset), .S(force_3FF), .CE(not_enable), .C(clk));

   MUXCY load_inc_carry_xhdl1_3 (.DI(1'b0), .CI(inc_load_value_carry[3 - 1]), .S(selected_load_value[3]), .O(inc_load_value_carry[3]));

   XORCY load_inc_xor_xhdl2_3 (.LI(selected_load_value[3]), .CI(inc_load_value_carry[3 - 1]), .O(inc_load_value[3]));

   MUXCY count_inc_carry_xhdl3_3 (.DI(1'b0), .CI(inc_count_value_carry[3 - 1]), .S(selected_count_value[3]), .O(inc_count_value_carry[3]));

   XORCY count_inc_xor_xhdl4_3 (.LI(selected_count_value[3]), .CI(inc_count_value_carry[3 - 1]), .O(inc_count_value[3]));

   mux2_LUT value_select_mux_4 (.D1(load_1_value[4]), .D0(load_0_value[4]), .sel(select_load_value), .Y(selected_load_value[4]));

   mux2_LUT count_select_mux_4 (.D1(count_value[4]), .D0(inc_load_value[4]), .sel(normal_count), .Y(selected_count_value[4]));