kcpsm2.v

和picoblaze完全兼容的mcu ip core

// Constant (K) Coded Programmable State Machine for Virtex-II Devices
//
// Verilog Version : 1.00
//            Date : July 2003
//
// Translation by Joel Coburn - Xilinx Inc.
//
// Derived from kcpsm2.vhd version 1.31 - 19th September 2002
//
// Ken Chapman
// Xilinx Ltd
// Benchmark House
// 203 Brooklands Road
// Weybridge
// Surrey KT13 ORH
// United Kingdom
//
// [e-mail]
//
//----------------------------------------------------------------------------------
//
// NOTICE:
//
// Copyright Xilinx, Inc. 2003.   This code may be contain portions patented by other 
// third parties.  By providing this core as one possible implementation of a standard,
// Xilinx is making no representation that the provided implementation of this standard 
// is free from any claims of infringement by any third party.  Xilinx expressly 
// disclaims any warranty with respect to the adequacy of the implementation, including 
// but not limited to any warranty or representation that the implementation is free 
// from claims of any third party.  Futhermore, Xilinx is providing this core as a 
// courtesy to you and suggests that you contact all third parties to obtain the 
// necessary rights to use this implementation.
//
//----------------------------------------------------------------------------------
//
// Format of this file.
//
// This file contains the definition of KCPSM2 and all the submodules which it requires. 
//
// The submodules define the implementation of the logic using Xilinx primitives.
// These ensure predictable synthesis results and maximise the density of the implementation. 
// The Unisim Library is used to define Xilinx primitives. It is also used during
// simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
// It is only specified in sub modules which contain primitive components.
// 
//----------------------------------------------------------------------------------
//
// Main Entity for KCPSM2
//
module kcpsm2 (address, instruction, port_id, write_strobe, out_port, read_strobe, in_port, interrupt, reset, clk);

   output[9:0] address; 
   wire[9:0] address;
   input[17:0] instruction; 
   output[7:0] port_id; 
   wire[7:0] port_id;
   output write_strobe; 
   wire write_strobe;
   output[7:0] out_port; 
   wire[7:0] out_port;
   output read_strobe; 
   wire read_strobe;
   input[7:0] in_port; 
   input interrupt; 
   input reset; 
   input clk; 

   wire T_state; 
   wire internal_reset; 
   wire[7:0] sX_register; 
   wire[7:0] sY_register; 
   wire register_write_enable; 
   wire[7:0] second_operand; 
   wire[7:0] logical_result; 
   wire[7:0] shift_and_rotate_result; 
   wire shift_and_rotate_carry; 
   wire[7:0] arithmetic_result; 
   wire arithmetic_carry; 
   wire[7:0] ALU_result; 
   wire carry_flag; 
   wire zero_flag; 
   wire flag_clock_enable; 
   wire flag_condition_met; 
   wire shaddow_carry_flag; 
   wire shaddow_zero_flag; 
   wire interrupt_enable; 
   wire active_interrupt; 
   wire[9:0] program_count; 
   wire[9:0] stack_pop_data; 
   wire[4:0] stack_pointer; 

   assign out_port = sX_register ;
   assign port_id = second_operand ;
   T_state_and_Reset basic_control (.reset_input(reset), .internal_reset(internal_reset), .T_state(T_state), .clk(clk)); 
   data_register_bank data_registers (.Address_A(instruction[12:8]), .Din_A_bus(ALU_result), .Write_A_bus(register_write_enable), .Dout_A_bus(sX_register), .Address_B(instruction[7:3]), .Dout_B_bus(sY_register), .clk(clk)); 
   zero_flag_logic zero (.data(ALU_result), .instruction17(instruction[17]), .instruction14(instruction[14]), .shadow_zero(shaddow_zero_flag), .reset(internal_reset), .flag_enable(flag_clock_enable), .zero_flag(zero_flag), .clk(clk)); 
   carry_flag_logic carry (.instruction17(instruction[17]), .instruction15(instruction[15]), .instruction14(instruction[14]), .shift_carry(shift_and_rotate_carry), .add_sub_carry(arithmetic_carry), .shadow_carry(shaddow_carry_flag), .reset(internal_reset), .flag_enable(flag_clock_enable), .carry_flag(carry_flag), .clk(clk)); 
   register_and_flag_enable reg_and_flag_enables (.instruction(instruction[17:13]), .active_interrupt(active_interrupt), .T_state(T_state), .register_enable(register_write_enable), .flag_enable(flag_clock_enable), .clk(clk)); 
   flag_test test_flags (.instruction11(instruction[11]), .instruction10(instruction[10]), .zero_flag(zero_flag), .carry_flag(carry_flag), .condition_met(flag_condition_met)); 
   data_bus_mux2 operand_select (.D1_bus(sY_register), .D0_bus(instruction[7:0]), .sel(instruction[16]), .Y_bus(second_operand)); 
   logical_bus_processing logical_group (.first_operand(sX_register), .second_operand(second_operand), .code1(instruction[14]), .code0(instruction[13]), .Y(logical_result), .clk(clk)); 
   arithmetic_process arithmetic_group (.first_operand(sX_register), .second_operand(second_operand), .carry_in(carry_flag), .code1(instruction[14]), .code0(instruction[13]), .Y(arithmetic_result), .carry_out(arithmetic_carry), .clk(clk)); 
   shift_rotate_process shift_group (.operand(sX_register), .carry_in(carry_flag), .inject_bit(instruction[0]), .shift_right(instruction[3]), .code1(instruction[2]), .code0(instruction[1]), .Y(shift_and_rotate_result), .carry_out(shift_and_rotate_carry), .clk(clk)); 
   data_bus_mux4 ALU_mux (.D3_bus(shift_and_rotate_result), .D2_bus(in_port), .D1_bus(arithmetic_result), .D0_bus(logical_result), .sel1(instruction[17]), .sel0(instruction[15]), .Y_bus(ALU_result)); 
   program_counter prog_count (.instruction17(instruction[17]), .instruction16(instruction[16]), .instruction15(instruction[15]), .instruction14(instruction[14]), .instruction12(instruction[12]), .low_instruction(instruction[9:0]), .stack_value(stack_pop_data), .flag_condition_met(flag_condition_met), .T_state(T_state), .reset(internal_reset), .force_3FF(active_interrupt), .program_count(program_count), .clk(clk)); 
   assign address = program_count ;
   stack_ram stack_memory (.Din(program_count), .Dout(stack_pop_data), .addr(stack_pointer), .write_bar(T_state), .clk(clk)); 
   stack_counter stack_control (.instruction17(instruction[17]), .instruction16(instruction[16]), .instruction14(instruction[14]), .instruction13(instruction[13]), .instruction12(instruction[12]), .T_state(T_state), .flag_condition_met(flag_condition_met), .active_interrupt(active_interrupt), .reset(internal_reset), .stack_count(stack_pointer), .clk(clk)); 
   IO_strobe_logic IO_strobes (.instruction17(instruction[17]), .instruction15(instruction[15]), .instruction14(instruction[14]), .instruction13(instruction[13]), .active_interrupt(active_interrupt), .T_state(T_state), .reset(internal_reset), .write_strobe(write_strobe), .read_strobe(read_strobe), .clk(clk)); 
   interrupt_capture get_interrupt (.interrupt(interrupt), .T_state(T_state), .reset(internal_reset), .interrupt_enable(interrupt_enable), .active_interrupt(active_interrupt), .clk(clk)); 
   interrupt_logic interrupt_control (.instruction17(instruction[17]), .instruction15(instruction[15]), .instruction14(instruction[14]), .instruction0(instruction[0]), .active_interrupt(active_interrupt), .carry_flag(carry_flag), .zero_flag(zero_flag), .reset(internal_reset), .interrupt_enable(interrupt_enable), .shaddow_carry(shaddow_carry_flag), .shaddow_zero(shaddow_zero_flag), .clk(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 8-bit adder/subtractor
//	
// This function uses 8 LUTs and associated MUXCY/XORCY components.
// The function contains an output pipeline register using 8 FDs.
// Total size is 4 slices.
//
//     subtract    Operation
//
//         0          ADD          Y <= first_operand + second_operand
//         1          SUB          Y <= first_operand - second_operand
//
//
module addsub8 (first_operand, second_operand, carry_in, subtract, Y, carry_out, clk);

   input[7:0] first_operand; 
   input[7:0] second_operand; 
   input carry_in; 
   input subtract; 
   output[7:0] Y; 
   wire[7:0] Y;
   output carry_out; 
   wire carry_out;
   input clk; 

   wire[7:0] half_addsub; 
   wire[7:0] full_addsub; 
   wire[6:0] carry_chain; 

   MUXCY arithmetic_carry_0 (.DI(first_operand[0]), .CI(carry_in), .S(half_addsub[0]), .O(carry_chain[0]));

   XORCY arithmetic_xor_0 (.LI(half_addsub[0]), .CI(carry_in), .O(full_addsub[0]));

   LUT3 arithmetic_lut_0(.I0(first_operand[0]), .I1(second_operand[0]), .I2(subtract), .O(half_addsub[0])); 
   // synthesis translate_off
   defparam arithmetic_lut_0.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_0 "96"
   FD pipeline_bit_0 (.D(full_addsub[0]), .Q(Y[0]), .C(clk));

   MUXCY arithmetic_carry_xhdl1_1 (.DI(first_operand[1]), .CI(carry_chain[1 - 1]), .S(half_addsub[1]), .O(carry_chain[1]));

   XORCY arithmetic_xor_xhdl2_1 (.LI(half_addsub[1]), .CI(carry_chain[1 - 1]), .O(full_addsub[1]));

   LUT3 arithmetic_lut_1(.I0(first_operand[1]), .I1(second_operand[1]), .I2(subtract), .O(half_addsub[1])); 
   // synthesis translate_off
   defparam arithmetic_lut_1.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_1 "96"
   FD pipeline_bit_1 (.D(full_addsub[1]), .Q(Y[1]), .C(clk));

   MUXCY arithmetic_carry_xhdl1_2 (.DI(first_operand[2]), .CI(carry_chain[2 - 1]), .S(half_addsub[2]), .O(carry_chain[2]));

   XORCY arithmetic_xor_xhdl2_2 (.LI(half_addsub[2]), .CI(carry_chain[2 - 1]), .O(full_addsub[2]));

   LUT3 arithmetic_lut_2(.I0(first_operand[2]), .I1(second_operand[2]), .I2(subtract), .O(half_addsub[2])); 
   // synthesis translate_off
   defparam arithmetic_lut_2.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_2 "96"
   FD pipeline_bit_2 (.D(full_addsub[2]), .Q(Y[2]), .C(clk));

   MUXCY arithmetic_carry_xhdl1_3 (.DI(first_operand[3]), .CI(carry_chain[3 - 1]), .S(half_addsub[3]), .O(carry_chain[3]));

   XORCY arithmetic_xor_xhdl2_3 (.LI(half_addsub[3]), .CI(carry_chain[3 - 1]), .O(full_addsub[3]));

   LUT3 arithmetic_lut_3(.I0(first_operand[3]), .I1(second_operand[3]), .I2(subtract), .O(half_addsub[3])); 
   // synthesis translate_off
   defparam arithmetic_lut_3.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_3 "96"
   FD pipeline_bit_3 (.D(full_addsub[3]), .Q(Y[3]), .C(clk));

   MUXCY arithmetic_carry_xhdl1_4 (.DI(first_operand[4]), .CI(carry_chain[4 - 1]), .S(half_addsub[4]), .O(carry_chain[4]));

   XORCY arithmetic_xor_xhdl2_4 (.LI(half_addsub[4]), .CI(carry_chain[4 - 1]), .O(full_addsub[4]));

   LUT3 arithmetic_lut_4(.I0(first_operand[4]), .I1(second_operand[4]), .I2(subtract), .O(half_addsub[4])); 
   // synthesis translate_off
   defparam arithmetic_lut_4.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_4 "96"
   FD pipeline_bit_4 (.D(full_addsub[4]), .Q(Y[4]), .C(clk));

   MUXCY arithmetic_carry_xhdl1_5 (.DI(first_operand[5]), .CI(carry_chain[5 - 1]), .S(half_addsub[5]), .O(carry_chain[5]));

   XORCY arithmetic_xor_xhdl2_5 (.LI(half_addsub[5]), .CI(carry_chain[5 - 1]), .O(full_addsub[5]));

   LUT3 arithmetic_lut_5(.I0(first_operand[5]), .I1(second_operand[5]), .I2(subtract), .O(half_addsub[5])); 
   // synthesis translate_off
   defparam arithmetic_lut_5.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_5 "96"
   FD pipeline_bit_5 (.D(full_addsub[5]), .Q(Y[5]), .C(clk));

   MUXCY arithmetic_carry_xhdl1_6 (.DI(first_operand[6]), .CI(carry_chain[6 - 1]), .S(half_addsub[6]), .O(carry_chain[6]));

   XORCY arithmetic_xor_xhdl2_6 (.LI(half_addsub[6]), .CI(carry_chain[6 - 1]), .O(full_addsub[6]));

   LUT3 arithmetic_lut_6(.I0(first_operand[6]), .I1(second_operand[6]), .I2(subtract), .O(half_addsub[6])); 
   // synthesis translate_off
   defparam arithmetic_lut_6.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_6 "96"
   FD pipeline_bit_6 (.D(full_addsub[6]), .Q(Y[6]), .C(clk));

   MUXCY arithmetic_carry_xhdl3_7 (.DI(first_operand[7]), .CI(carry_chain[7 - 1]), .S(half_addsub[7]), .O(carry_out));

   XORCY arithmetic_xor_xhdl4_7 (.LI(half_addsub[7]), .CI(carry_chain[7 - 1]), .O(full_addsub[7]));

   LUT3 arithmetic_lut_7(.I0(first_operand[7]), .I1(second_operand[7]), .I2(subtract), .O(half_addsub[7])); 
   // synthesis translate_off
   defparam arithmetic_lut_7.INIT = 8'h96;
   // synthesis translate_on
   // synthesis attribute INIT of arithmetic_lut_7 "96"
   FD pipeline_bit_7 (.D(full_addsub[7]), .Q(Y[7]), .C(clk)); 
endmodule

//----------------------------------------------------------------------------------
//
// Definition of an 8-bit arithmetic process
//	
// This function uses 10 LUTs and associated carry logic.
// The function contains an output pipeline register using 9 FDs.
//
// Operation
//
// Two input operands are added or subtracted.
// An input carry bit can be included in the calculation.
// An output carry is always generated.
// Carry signals work in the positive sense at all times.
//
//     code1     code0         Bit injected
//
//       0        0            ADD           
//       0        1            ADD with carry 
//       1        0            SUB  
//       1        1            SUB with carry 
//
//
module arithmetic_process (first_operand, second_operand, carry_in, code1, code0, Y, carry_out, clk);

   input[7:0] first_operand; 
   input[7:0] second_operand; 
   input carry_in; 
   input code1; 
   input code0; 
   output[7:0] Y; 
   wire[7:0] Y;
   output carry_out; 
   wire carry_out;
   input clk; 

   wire carry_in_bit; 
   wire carry_out_bit; 
   wire modified_carry_out; 
 
   LUT3 carry_input_lut(.I0(carry_in), .I1(code0), .I2(code1), .O(carry_in_bit)); 
   // synthesis translate_off
   defparam carry_input_lut.INIT = 8'h78;
   // synthesis translate_on
   // synthesis attribute INIT of carry_input_lut "78" 
   addsub8 add_sub_module (.first_operand(first_operand), .second_operand(second_operand), .carry_in(carry_in_bit), .subtract(code1), .Y(Y), .carry_out(carry_out_bit), .clk(clk)); 

   LUT2 carry_output_lut(.I0(carry_out_bit), .I1(code1), .O(modified_carry_out)); 
   // synthesis translate_off
   defparam carry_output_lut.INIT = 4'h6;
   // synthesis translate_on
   // synthesis attribute INIT of carry_output_lut "6"
   FD pipeline_bit (.D(modified_carry_out), .Q(carry_out), .C(clk));