📄 frequencycount_vhd.sdo

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      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst4\|COUNT\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (576:576:576) (576:576:576))
        (PORT datac (581:581:581) (581:581:581))
        (PORT datad (587:587:587) (587:587:587))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst4\|COUNT\[2\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1059:1059:1059) (1059:1059:1059))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst4\|COUNT\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4557:4557:4557) (4557:4557:4557))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst4\|COUNT\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (576:576:576) (576:576:576))
        (PORT datab (542:542:542) (542:542:542))
        (PORT datac (587:587:587) (587:587:587))
        (PORT datad (584:584:584) (584:584:584))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst4\|COUNT\[1\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1065:1065:1065) (1065:1065:1065))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst4\|COUNT\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4557:4557:4557) (4557:4557:4557))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst4\|COUNT\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (577:577:577) (577:577:577))
        (PORT datab (543:543:543) (543:543:543))
        (PORT datac (582:582:582) (582:582:582))
        (PORT datad (589:589:589) (589:589:589))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst4\|COUNT\[3\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1060:1060:1060) (1060:1060:1060))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst4\|COUNT\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4557:4557:4557) (4557:4557:4557))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst4\|CLK_OUT\~95_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (541:541:541) (541:541:541))
        (PORT datac (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\CLK_SE\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\SEL\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1475:1475:1475) (1475:1475:1475))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|EN\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (513:513:513) (513:513:513))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst\|EN\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1957:1957:1957) (1957:1957:1957))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|NUM\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (533:533:533) (533:533:533))
        (PORT datab (674:674:674) (674:674:674))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst\|NUM\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2792:2792:2792) (2792:2792:2792))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4369:4369:4369) (4369:4369:4369))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|NUM\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (506:506:506) (506:506:506))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst\|NUM\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2792:2792:2792) (2792:2792:2792))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4369:4369:4369) (4369:4369:4369))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|NUM\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (514:514:514) (514:514:514))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst\|NUM\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2792:2792:2792) (2792:2792:2792))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4369:4369:4369) (4369:4369:4369))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|NUM\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (505:505:505) (505:505:505))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst\|NUM\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2792:2792:2792) (2792:2792:2792))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4369:4369:4369) (4369:4369:4369))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|NUM\[4\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (534:534:534) (534:534:534))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst\|NUM\[4\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2792:2792:2792) (2792:2792:2792))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4369:4369:4369) (4369:4369:4369))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|NUM\[5\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (534:534:534) (534:534:534))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst\|NUM\[5\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2792:2792:2792) (2792:2792:2792))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4369:4369:4369) (4369:4369:4369))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst\|NUM\[6\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (520:520:520) (520:520:520))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
💿 文件大小 591 K
👤 上传用户 Kunlun_mrpii
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #频率计
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