frequencycount_vhd.sdo

FPGA设计频率计全套资料

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C3T144C8 Package TQFP144
// 

// 
// This SDF file should be used for PrimeTime (VHDL) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "frequencycount")
  (DATE "08/01/2007 15:16:50")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst10\|CLKN\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (536:536:536) (536:536:536))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst10\|CLKN\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1014:1014:1014) (1014:1014:1014))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst10\|CLKN\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1597:1597:1597) (1597:1597:1597))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst5\|CLK_OUT\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (538:538:538) (538:538:538))
        (PORT datab (401:401:401) (401:401:401))
        (PORT datac (609:609:609) (609:609:609))
        (PORT datad (567:567:567) (567:567:567))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst5\|CLK_OUT\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst5\|CLK_OUT\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4878:4878:4878) (4878:4878:4878))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\20mclk\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst2\|Selector11\~81_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (796:796:796) (796:796:796))
        (PORT datac (2608:2608:2608) (2608:2608:2608))
        (PORT datad (776:776:776) (776:776:776))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst2\|Selector11\~82_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (547:547:547) (547:547:547))
        (PORT datab (547:547:547) (547:547:547))
        (PORT datac (1140:1140:1140) (1140:1140:1140))
        (PORT datad (791:791:791) (791:791:791))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst4\|CLK_OUT\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (577:577:577) (577:577:577))
        (PORT datab (400:400:400) (400:400:400))
        (PORT datac (563:563:563) (563:563:563))
        (PORT datad (590:590:590) (590:590:590))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst4\|CLK_OUT\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1041:1041:1041) (1041:1041:1041))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst4\|CLK_OUT\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4557:4557:4557) (4557:4557:4557))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst2\|Selector11\~83_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (565:565:565) (565:565:565))
        (PORT datab (1249:1249:1249) (1249:1249:1249))
        (PORT datac (2278:2278:2278) (2278:2278:2278))
        (PORT datad (541:541:541) (541:541:541))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst2\|Selector11\~84_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1076:1076:1076) (1076:1076:1076))
        (PORT datab (4151:4151:4151) (4151:4151:4151))
        (PORT datac (733:733:733) (733:733:733))
        (PORT datad (182:182:182) (182:182:182))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst5\|COUNT\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (607:607:607) (607:607:607))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst5\|COUNT\[0\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1085:1085:1085) (1085:1085:1085))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst5\|COUNT\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4878:4878:4878) (4878:4878:4878))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst5\|COUNT\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (564:564:564) (564:564:564))
        (PORT datab (585:585:585) (585:585:585))
        (PORT datac (601:601:601) (601:601:601))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst5\|COUNT\[2\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1079:1079:1079) (1079:1079:1079))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst5\|COUNT\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4878:4878:4878) (4878:4878:4878))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst5\|COUNT\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (554:554:554) (554:554:554))
        (PORT datab (568:568:568) (568:568:568))
        (PORT datac (609:609:609) (609:609:609))
        (PORT datad (564:564:564) (564:564:564))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst5\|COUNT\[1\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst5\|COUNT\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4878:4878:4878) (4878:4878:4878))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst5\|COUNT\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (553:553:553) (553:553:553))
        (PORT datab (567:567:567) (567:567:567))
        (PORT datac (607:607:607) (607:607:607))
        (PORT datad (565:565:565) (565:565:565))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\inst5\|COUNT\[3\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1085:1085:1085) (1085:1085:1085))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst5\|COUNT\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4878:4878:4878) (4878:4878:4878))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst5\|CLK_OUT\~95_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (569:569:569) (569:569:569))
        (PORT datac (569:569:569) (569:569:569))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst4\|COUNT\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (579:579:579) (579:579:579))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst4\|COUNT\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4557:4557:4557) (4557:4557:4557))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK