frequencycount.vho

FPGA设计频率计全套资料

SIGNAL \inst13|TEMP[2]\ : std_logic;
SIGNAL \inst13|TEMP[1]\ : std_logic;
SIGNAL \inst13|TEMP[0]\ : std_logic;
SIGNAL \inst13|Q\ : std_logic;
SIGNAL \inst2|WideOr12\ : std_logic;
SIGNAL \inst11|COUNT[0]\ : std_logic;
SIGNAL \inst11|COUNT[3]\ : std_logic;
SIGNAL \inst11|COUNT[1]\ : std_logic;
SIGNAL \inst11|COUNT[2]\ : std_logic;
SIGNAL \inst11|CLK_OUT~95\ : std_logic;
SIGNAL \inst11|CLK_OUT\ : std_logic;
SIGNAL \inst14|Add0~103\ : std_logic;
SIGNAL \inst14|Equal0~36\ : std_logic;
SIGNAL \inst14|COUNT~169\ : std_logic;
SIGNAL \inst14|COUNT[3]\ : std_logic;
SIGNAL \inst14|Equal0~37\ : std_logic;
SIGNAL \inst14|EN\ : std_logic;
SIGNAL \inst14|COUNT[0]\ : std_logic;
SIGNAL \inst14|COUNT[1]\ : std_logic;
SIGNAL \inst14|COUNT[2]\ : std_logic;
SIGNAL \inst14|process2~29\ : std_logic;
SIGNAL \inst14|POT~69\ : std_logic;
SIGNAL \inst14|POT\ : std_logic;
SIGNAL \inst14|ALT_INV_POT\ : std_logic;
SIGNAL \inst10|ALT_INV_CLKN\ : std_logic;
SIGNAL \inst|ALT_INV_ENTRANSFER\ : std_logic;
SIGNAL \inst|ALT_INV_EN\ : std_logic;
SIGNAL \ALT_INV_SEL~combout\ : std_logic;
COMPONENT cyclone_lcell
PORT (
	clk : IN STD_LOGIC;
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	enable_asynch_arcs : IN STD_LOGIC);
END COMPONENT;

COMPONENT cyclone_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(26 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

Q <= ww_Q;
ww_CLK_SE <= CLK_SE;
ww_SEL <= SEL;
ww_RESET <= RESET;
\ww_20mclk\ <= \20mclk\;
ww_CLK_TEST <= CLK_TEST;
FRECODE <= ww_FRECODE;
PULSEINT <= ww_PULSEINT;
CLK <= ww_CLK;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\inst10|CLKN~I_modesel\ <= "1100001010101";
\inst10|CLKN~I_pathsel\ <= "00000000100";
\inst5|CLK_OUT~I_modesel\ <= "1100001010101";
\inst5|CLK_OUT~I_pathsel\ <= "00000001111";
\20mclk~I_modesel\ <= "000000000000000000000000001";
\inst2|Selector11~81_I_modesel\ <= "1001001010101";
\inst2|Selector11~81_I_pathsel\ <= "00000001110";
\inst2|Selector11~82_I_modesel\ <= "1001001010101";
\inst2|Selector11~82_I_pathsel\ <= "00000001111";
\inst4|CLK_OUT~I_modesel\ <= "1100001010101";
\inst4|CLK_OUT~I_pathsel\ <= "00000001111";
\inst2|Selector11~83_I_modesel\ <= "1001001010101";
\inst2|Selector11~83_I_pathsel\ <= "00000001111";
\inst2|Selector11~84_I_modesel\ <= "1001001010101";
\inst2|Selector11~84_I_pathsel\ <= "00000001111";
\inst5|COUNT[0]~I_modesel\ <= "1100001010101";
\inst5|COUNT[0]~I_pathsel\ <= "00000000100";
\inst5|COUNT[2]~I_modesel\ <= "1100001010101";
\inst5|COUNT[2]~I_pathsel\ <= "00000000111";
\inst5|COUNT[1]~I_modesel\ <= "1100001010101";
\inst5|COUNT[1]~I_pathsel\ <= "00000001111";
\inst5|COUNT[3]~I_modesel\ <= "1100001010101";
\inst5|COUNT[3]~I_pathsel\ <= "00000001111";
\inst5|CLK_OUT~95_I_modesel\ <= "1001001010101";
\inst5|CLK_OUT~95_I_pathsel\ <= "00000000110";
\inst4|COUNT[0]~I_modesel\ <= "1100001010101";
\inst4|COUNT[0]~I_pathsel\ <= "00000001000";
\inst4|COUNT[2]~I_modesel\ <= "1100001010101";
\inst4|COUNT[2]~I_pathsel\ <= "00000001101";
\inst4|COUNT[1]~I_modesel\ <= "1100001010101";
\inst4|COUNT[1]~I_pathsel\ <= "00000001111";
\inst4|COUNT[3]~I_modesel\ <= "1100001010101";
\inst4|COUNT[3]~I_pathsel\ <= "00000001111";
\inst4|CLK_OUT~95_I_modesel\ <= "1001001010101";
\inst4|CLK_OUT~95_I_pathsel\ <= "00000000110";
\CLK_SE~I_modesel\ <= "000000000000000000000000001";
\SEL~I_modesel\ <= "000000000000000000000000001";
\inst|EN~I_modesel\ <= "1100001010101";
\inst|EN~I_pathsel\ <= "00000001000";
\inst|NUM[0]~I_modesel\ <= "1100001011010";
\inst|NUM[0]~I_pathsel\ <= "00110000011";
\inst|NUM[1]~I_modesel\ <= "1100010011010";
\inst|NUM[1]~I_pathsel\ <= "01100010010";
\inst|NUM[2]~I_modesel\ <= "1100010011010";
\inst|NUM[2]~I_pathsel\ <= "01100010010";
\inst|NUM[3]~I_modesel\ <= "1100010011010";
\inst|NUM[3]~I_pathsel\ <= "01100010010";
\inst|NUM[4]~I_modesel\ <= "1100010011010";
\inst|NUM[4]~I_pathsel\ <= "01010010001";
\inst|NUM[5]~I_modesel\ <= "1100010011010";
\inst|NUM[5]~I_pathsel\ <= "01010010001";
\inst|NUM[6]~I_modesel\ <= "1100010011010";
\inst|NUM[6]~I_pathsel\ <= "01100010010";
\inst|NUM[7]~I_modesel\ <= "1100010011010";
\inst|NUM[7]~I_pathsel\ <= "01010010001";
\inst|NUM[8]~I_modesel\ <= "1100010011010";
\inst|NUM[8]~I_pathsel\ <= "01100010010";
\inst|NUM[9]~I_modesel\ <= "1100010011010";
\inst|NUM[9]~I_pathsel\ <= "01010010001";
\inst|NUM[10]~I_modesel\ <= "1100010011010";
\inst|NUM[10]~I_pathsel\ <= "01010010001";
\inst|NUM[11]~I_modesel\ <= "1100010011010";
\inst|NUM[11]~I_pathsel\ <= "01100010010";
\inst|NUM[12]~I_modesel\ <= "1100010011010";
\inst|NUM[12]~I_pathsel\ <= "01100010010";
\inst|NUM[13]~I_modesel\ <= "1100010011010";
\inst|NUM[13]~I_pathsel\ <= "01100010010";
\inst|NUM[14]~I_modesel\ <= "1100010011010";
\inst|NUM[14]~I_pathsel\ <= "01010010001";
\inst|NUM[15]~I_modesel\ <= "1100010011010";
\inst|NUM[15]~I_pathsel\ <= "01010010001";
\inst|NUM[16]~I_modesel\ <= "1100010011001";
\inst|NUM[16]~I_pathsel\ <= "00000010010";
\inst|Equal0~146_I_modesel\ <= "1001001010101";
\inst|Equal0~146_I_pathsel\ <= "00000001111";
\inst|Equal0~145_I_modesel\ <= "1001001010101";
\inst|Equal0~145_I_pathsel\ <= "00000001111";
\inst|Equal0~142_I_modesel\ <= "1001001010101";
\inst|Equal0~142_I_pathsel\ <= "00000001100";
\inst|Equal0~143_I_modesel\ <= "1001001010101";
\inst|Equal0~143_I_pathsel\ <= "00000001111";
\inst|Equal0~144_I_modesel\ <= "1001001010101";
\inst|Equal0~144_I_pathsel\ <= "00000001111";
\inst|Equal0~147_I_modesel\ <= "1001001010101";
\inst|Equal0~147_I_pathsel\ <= "00000001111";
\inst|NUMH[13]~688_I_modesel\ <= "1001001010101";
\inst|NUMH[13]~688_I_pathsel\ <= "00000001100";
\inst|ENTRANSFER~I_modesel\ <= "1100001011001";
\inst|ENTRANSFER~I_pathsel\ <= "00000000000";
\inst|LessThan0~208_I_modesel\ <= "1001001010101";
\inst|LessThan0~208_I_pathsel\ <= "00000001111";
\inst|LessThan0~209_I_modesel\ <= "1001001010101";
\inst|LessThan0~209_I_pathsel\ <= "00000001111";
\inst|LessThan0~207_I_modesel\ <= "1001001010101";
\inst|LessThan0~207_I_pathsel\ <= "00000001110";
\inst|LessThan0~210_I_modesel\ <= "1001001010101";
\inst|LessThan0~210_I_pathsel\ <= "00000001111";
\inst|LOW~I_modesel\ <= "1100001011001";
\inst|LOW~I_pathsel\ <= "00000001111";
\inst3|LOCK~I_modesel\ <= "1100001010101";
\inst3|LOCK~I_pathsel\ <= "00000001000";
\inst3|SIGOUT~I_modesel\ <= "1100001010101";
\inst3|SIGOUT~I_pathsel\ <= "00000001100";
\inst|OVER~I_modesel\ <= "1100001011001";
\inst|OVER~I_pathsel\ <= "00000001110";
\inst12|LOCK~I_modesel\ <= "1100001010101";
\inst12|LOCK~I_pathsel\ <= "00000001000";
\inst12|SIGOUT~I_modesel\ <= "1100001010101";
\inst12|SIGOUT~I_pathsel\ <= "00000001100";
\inst2|Selector0~58_I_modesel\ <= "1001001010101";
\inst2|Selector0~58_I_pathsel\ <= "00000001111";
\RESET~I_modesel\ <= "000000000000000000000000001";
\inst2|STATE.f10m~I_modesel\ <= "1100001010101";
\inst2|STATE.f10m~I_pathsel\ <= "00000000001";
\inst2|Selector1~59_I_modesel\ <= "1001001010101";
\inst2|Selector1~59_I_pathsel\ <= "00000001111";
\inst2|STATE.p10s~I_modesel\ <= "1100001010101";
\inst2|STATE.p10s~I_pathsel\ <= "00000001111";
\inst2|STATE.overflowl~I_modesel\ <= "1100001010101";
\inst2|STATE.overflowl~I_pathsel\ <= "00000001111";
\inst2|Selector6~54_I_modesel\ <= "1001001010101";
\inst2|Selector6~54_I_pathsel\ <= "00000001111";
\inst2|Selector6~55_I_modesel\ <= "1001001010101";
\inst2|Selector6~55_I_pathsel\ <= "00000001100";
\inst2|STATE.p1s~I_modesel\ <= "1100001010101";
\inst2|STATE.p1s~I_pathsel\ <= "00000001111";
\inst2|Selector5~43_I_modesel\ <= "1001001010101";
\inst2|Selector5~43_I_pathsel\ <= "00000001111";
\inst2|STATE.p100ms~I_modesel\ <= "1100001010101";
\inst2|STATE.p100ms~I_pathsel\ <= "00000001101";
\inst2|Selector4~68_I_modesel\ <= "1001001010101";
\inst2|Selector4~68_I_pathsel\ <= "00000001111";
\inst2|STATE.p10ms~I_modesel\ <= "1100001010101";
\inst2|STATE.p10ms~I_pathsel\ <= "00000001111";
\inst2|STATE.p1ms~I_modesel\ <= "1100001010101";
\inst2|STATE.p1ms~I_pathsel\ <= "00000001111";
\inst2|Selector2~64_I_modesel\ <= "1001001010101";
\inst2|Selector2~64_I_pathsel\ <= "00000001010";
\inst2|STATE.f100k~I_modesel\ <= "1100001010101";
\inst2|STATE.f100k~I_pathsel\ <= "00000001111";
\inst2|Selector1~60_I_modesel\ <= "1001001010101";
\inst2|Selector1~60_I_pathsel\ <= "00000001100";
\inst2|STATE.overflowh~I_modesel\ <= "1100001010101";
\inst2|STATE.overflowh~I_pathsel\ <= "00000001111";
\inst2|STATE.f1m~I_modesel\ <= "1100001010101";
\inst2|STATE.f1m~I_pathsel\ <= "00000001111";
\inst8|COUNT[0]~I_modesel\ <= "1100001010101";
\inst8|COUNT[0]~I_pathsel\ <= "00000001000";
\inst8|COUNT[2]~I_modesel\ <= "1100001010101";
\inst8|COUNT[2]~I_pathsel\ <= "00000001101";
\inst8|COUNT[3]~I_modesel\ <= "1100001010101";
\inst8|COUNT[3]~I_pathsel\ <= "00000001111";
\inst8|COUNT[1]~I_modesel\ <= "1100001010101";
\inst8|COUNT[1]~I_pathsel\ <= "00000001111";
\inst8|CLK_OUT~95_I_modesel\ <= "1001001010101";
\inst8|CLK_OUT~95_I_pathsel\ <= "00000001100";
\inst8|CLK_OUT~I_modesel\ <= "1100001010101";
\inst8|CLK_OUT~I_pathsel\ <= "00000001111";