frequencycount.vho

FPGA设计频率计全套资料

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

-- DATE "08/01/2007 15:16:50"

-- 
-- Device: Altera EP1C3T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	frequencycount IS
    PORT (
	Q : OUT std_logic;
	CLK_SE : IN std_logic;
	SEL : IN std_logic;
	RESET : IN std_logic;
	\20mclk\ : IN std_logic;
	CLK_TEST : IN std_logic;
	FRECODE : OUT std_logic_vector(2 DOWNTO 0);
	PULSEINT : OUT std_logic;
	CLK : OUT std_logic
	);
END frequencycount;

ARCHITECTURE structure OF frequencycount IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_Q : std_logic;
SIGNAL ww_CLK_SE : std_logic;
SIGNAL ww_SEL : std_logic;
SIGNAL ww_RESET : std_logic;
SIGNAL \ww_20mclk\ : std_logic;
SIGNAL ww_CLK_TEST : std_logic;
SIGNAL ww_FRECODE : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_PULSEINT : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL \inst10|CLKN~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst10|CLKN~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst5|CLK_OUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst5|CLK_OUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \20mclk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst2|Selector11~81_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector11~81_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector11~82_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector11~82_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|CLK_OUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|CLK_OUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector11~83_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector11~83_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector11~84_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector11~84_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst5|COUNT[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst5|COUNT[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst5|COUNT[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst5|COUNT[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst5|COUNT[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst5|COUNT[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst5|COUNT[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst5|COUNT[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst5|CLK_OUT~95_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst5|CLK_OUT~95_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|COUNT[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|COUNT[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|COUNT[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|COUNT[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|COUNT[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|COUNT[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|COUNT[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|COUNT[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|CLK_OUT~95_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|CLK_OUT~95_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \CLK_SE~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \SEL~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst|EN~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|EN~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUM[16]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUM[16]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|Equal0~146_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|Equal0~146_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|Equal0~145_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|Equal0~145_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|Equal0~142_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|Equal0~142_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|Equal0~143_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|Equal0~143_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|Equal0~144_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|Equal0~144_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|Equal0~147_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|Equal0~147_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|NUMH[13]~688_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|NUMH[13]~688_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|ENTRANSFER~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|ENTRANSFER~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|LessThan0~208_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|LessThan0~208_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|LessThan0~209_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|LessThan0~209_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|LessThan0~207_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|LessThan0~207_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|LessThan0~210_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|LessThan0~210_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|LOW~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|LOW~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|LOCK~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|LOCK~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|SIGOUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|SIGOUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|OVER~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|OVER~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst12|LOCK~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst12|LOCK~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst12|SIGOUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst12|SIGOUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector0~58_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector0~58_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \RESET~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst2|STATE.f10m~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.f10m~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector1~59_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector1~59_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.p10s~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.p10s~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.overflowl~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.overflowl~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector6~54_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector6~54_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector6~55_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector6~55_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.p1s~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.p1s~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector5~43_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector5~43_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.p100ms~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.p100ms~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector4~68_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector4~68_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.p10ms~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.p10ms~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.p1ms~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.p1ms~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector2~64_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector2~64_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.f100k~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.f100k~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector1~60_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector1~60_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.overflowh~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.overflowh~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|STATE.f1m~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|STATE.f1m~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst8|COUNT[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst8|COUNT[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst8|COUNT[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst8|COUNT[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst8|COUNT[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst8|COUNT[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst8|COUNT[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst8|COUNT[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst8|CLK_OUT~95_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst8|CLK_OUT~95_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst8|CLK_OUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst8|CLK_OUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst6|COUNT[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst6|COUNT[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst6|COUNT[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst6|COUNT[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst6|COUNT[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst6|COUNT[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst6|COUNT[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst6|COUNT[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst6|CLK_OUT~89_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst6|CLK_OUT~89_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst6|CLK_OUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst6|CLK_OUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst7|COUNT[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst7|COUNT[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst7|COUNT[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst7|COUNT[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst7|COUNT[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst7|COUNT[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst7|COUNT[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst7|COUNT[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst7|CLK_OUT~95_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst7|CLK_OUT~95_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst7|CLK_OUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst7|CLK_OUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|Selector10~75_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|Selector10~75_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|COUNT[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|COUNT[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|COUNT[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|COUNT[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|COUNT[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|COUNT[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|COUNT[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|COUNT[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|CLK_OUT~95_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|CLK_OUT~95_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|CLK_OUT~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|CLK_OUT~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst9|COUNT[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst9|COUNT[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);