frequencycount.vo

FPGA设计频率计全套资料

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "08/01/2007 15:16:49"

// 
// Device: Altera EP1C3T144C8 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module frequencycount (
	Q,
	CLK_SE,
	SEL,
	RESET,
	\20mclk ,
	CLK_TEST,
	FRECODE,
	PULSEINT,
	CLK);
output 	Q;
input 	CLK_SE;
input 	SEL;
input 	RESET;
input 	\20mclk ;
input 	CLK_TEST;
output 	[2:0] FRECODE;
output 	PULSEINT;
output 	CLK;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("frequencycount_v.sdo");
// synopsys translate_on

wire \inst10|CLKN ;
wire \inst5|CLK_OUT ;
wire \inst2|Selector11~81 ;
wire \inst2|Selector11~82 ;
wire \inst4|CLK_OUT ;
wire \inst2|Selector11~83 ;
wire \inst2|Selector11~84 ;
wire \inst5|CLK_OUT~95 ;
wire \inst4|CLK_OUT~95 ;
wire \20mclk~combout ;
wire \CLK_SE~combout ;
wire \SEL~combout ;
wire \inst|EN ;
wire \inst|NUM[0]~205 ;
wire \inst|NUM[0]~205COUT1_218 ;
wire \inst|NUM[1]~206 ;
wire \inst|NUM[1]~206COUT1_219 ;
wire \inst|NUM[2]~211 ;
wire \inst|NUM[3]~212 ;
wire \inst|NUM[3]~212COUT1_220 ;
wire \inst|NUM[4]~207 ;
wire \inst|NUM[4]~207COUT1_221 ;
wire \inst|NUM[5]~209 ;
wire \inst|NUM[5]~209COUT1_222 ;
wire \inst|NUM[6]~208 ;
wire \inst|NUM[6]~208COUT1_223 ;
wire \inst|NUM[7]~210 ;
wire \inst|NUM[8]~214 ;
wire \inst|NUM[8]~214COUT1_224 ;
wire \inst|NUM[9]~203 ;
wire \inst|NUM[9]~203COUT1_225 ;
wire \inst|NUM[10]~204 ;
wire \inst|NUM[10]~204COUT1_226 ;
wire \inst|NUM[11]~201 ;
wire \inst|NUM[11]~201COUT1_227 ;
wire \inst|NUM[12]~202 ;
wire \inst|NUM[13]~215 ;
wire \inst|NUM[13]~215COUT1_228 ;
wire \inst|NUM[14]~216 ;
wire \inst|NUM[14]~216COUT1_229 ;
wire \inst|NUM[15]~213 ;
wire \inst|NUM[15]~213COUT1_230 ;
wire \inst|Equal0~146 ;
wire \inst|Equal0~145 ;
wire \inst|Equal0~142 ;
wire \inst|Equal0~143 ;
wire \inst|Equal0~144 ;
wire \inst|Equal0~147 ;
wire \inst|NUMH[13]~688 ;
wire \inst|ENTRANSFER ;
wire \inst|LessThan0~208 ;
wire \inst|LessThan0~209 ;
wire \inst|LessThan0~207 ;
wire \inst|LessThan0~210 ;
wire \inst|LOW ;
wire \inst3|LOCK ;
wire \inst3|SIGOUT ;
wire \inst|OVER ;
wire \inst12|LOCK ;
wire \inst12|SIGOUT ;
wire \inst2|Selector0~58 ;
wire \RESET~combout ;
wire \inst2|STATE.f10m ;
wire \inst2|Selector1~59 ;
wire \inst2|STATE.p10s ;
wire \inst2|STATE.overflowl ;
wire \inst2|Selector6~54 ;
wire \inst2|Selector6~55 ;
wire \inst2|STATE.p1s ;
wire \inst2|Selector5~43 ;
wire \inst2|STATE.p100ms ;
wire \inst2|Selector4~68 ;
wire \inst2|STATE.p10ms ;
wire \inst2|STATE.p1ms ;
wire \inst2|Selector2~64 ;
wire \inst2|STATE.f100k ;
wire \inst2|Selector1~60 ;
wire \inst2|STATE.overflowh ;
wire \inst2|STATE.f1m ;
wire \inst8|CLK_OUT~95 ;
wire \inst8|CLK_OUT ;
wire \inst6|CLK_OUT~89 ;
wire \inst6|CLK_OUT ;
wire \inst7|CLK_OUT~95 ;
wire \inst7|CLK_OUT ;
wire \inst2|Selector10~75 ;
wire \inst1|CLK_OUT~95 ;
wire \inst1|CLK_OUT ;
wire \inst9|CLK_OUT~95 ;
wire \inst9|CLK_OUT ;
wire \inst2|Selector10~72 ;
wire \CLK_TEST~combout ;
wire \inst2|Selector10~73 ;
wire \inst2|Selector10~74 ;
wire \inst2|Selector10~76 ;
wire \inst|NUMH[0]~689 ;
wire \inst|NUMH[0]~689COUT1_706 ;
wire \inst|RESULTH[1]~18 ;
wire \inst|NUMH[1]~687 ;
wire \inst|NUMH[1]~687COUT1_707 ;
wire \inst|NUMH[2]~690 ;
wire \inst|NUMH[3]~691 ;
wire \inst|NUMH[3]~691COUT1_708 ;
wire \inst|NUMH[4]~692 ;
wire \inst|NUMH[4]~692COUT1_709 ;
wire \inst|NUMH[5]~693 ;
wire \inst|NUMH[5]~693COUT1_710 ;
wire \inst|NUMH[6]~694 ;
wire \inst|NUMH[6]~694COUT1_711 ;
wire \inst|NUMH[7]~695 ;
wire \inst|NUMH[8]~696 ;
wire \inst|NUMH[8]~696COUT1_712 ;
wire \inst|NUMH[9]~697 ;
wire \inst|NUMH[9]~697COUT1_713 ;
wire \inst2|WideOr12~12 ;
wire \inst2|WideOr13 ;
wire \inst2|WideOr12~13 ;
wire \inst2|WideOr14 ;
wire \inst|NUMH[10]~698 ;
wire \inst|NUMH[10]~698COUT1_714 ;
wire \inst|NUMH[11]~699 ;
wire \inst|NUMH[11]~699COUT1_715 ;
wire \inst|NUMH[12]~700 ;
wire \inst|NUMH[13]~701 ;
wire \inst|NUMH[13]~701COUT1_716 ;
wire \inst|NUMH[14]~702 ;
wire \inst|NUMH[14]~702COUT1_717 ;
wire \inst|NUMH[15]~703 ;
wire \inst|NUMH[15]~703COUT1_718 ;
wire \inst13|Q ;
wire \inst2|WideOr12 ;
wire \inst11|CLK_OUT~95 ;
wire \inst11|CLK_OUT ;
wire \inst14|Add0~103 ;
wire \inst14|Equal0~36 ;
wire \inst14|COUNT~169 ;
wire \inst14|Equal0~37 ;
wire \inst14|EN ;
wire \inst14|process2~29 ;
wire \inst14|POT~69 ;
wire \inst14|POT ;
wire [3:0] \inst14|COUNT ;
wire [3:0] \inst1|COUNT ;
wire [16:0] \inst|NUM ;
wire [16:0] \inst|NUMH ;
wire [16:0] \inst|RESULT ;
wire [16:0] \inst|RESULTH ;
wire [39:0] \inst13|TEMP ;
wire [3:0] \inst11|COUNT ;
wire [3:0] \inst4|COUNT ;
wire [3:0] \inst5|COUNT ;
wire [3:0] \inst6|COUNT ;
wire [3:0] \inst7|COUNT ;
wire [3:0] \inst8|COUNT ;
wire [3:0] \inst9|COUNT ;


// atom is at LC_X8_Y6_N2
cyclone_lcell \inst10|CLKN~I (
// Equation(s):
// \inst10|CLKN  = DFFEAS(!\inst10|CLKN , \20mclk~combout , VCC, , , , , , )

	.clk(\20mclk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\inst10|CLKN ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst10|CLKN ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst10|CLKN~I .lut_mask = "0F0F";
defparam \inst10|CLKN~I .operation_mode = "normal";
defparam \inst10|CLKN~I .output_mode = "reg_only";
defparam \inst10|CLKN~I .register_cascade_mode = "off";
defparam \inst10|CLKN~I .sum_lutc_input = "datac";
defparam \inst10|CLKN~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y6_N2
cyclone_lcell \inst5|CLK_OUT~I (
// Equation(s):
// \inst5|CLK_OUT  = DFFEAS(\inst5|CLK_OUT  & (\inst5|CLK_OUT~95  # \inst5|COUNT [0] # \inst5|COUNT [2]) # !\inst5|CLK_OUT  & !\inst5|CLK_OUT~95  & \inst5|COUNT [0] & \inst5|COUNT [2], GLOBAL(\inst4|CLK_OUT ), VCC, , , , , , )

	.clk(\inst4|CLK_OUT ),
	.dataa(\inst5|CLK_OUT ),
	.datab(\inst5|CLK_OUT~95 ),
	.datac(\inst5|COUNT [0]),
	.datad(\inst5|COUNT [2]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst5|CLK_OUT ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst5|CLK_OUT~I .lut_mask = "BAA8";
defparam \inst5|CLK_OUT~I .operation_mode = "normal";
defparam \inst5|CLK_OUT~I .output_mode = "reg_only";
defparam \inst5|CLK_OUT~I .register_cascade_mode = "off";
defparam \inst5|CLK_OUT~I .sum_lutc_input = "datac";
defparam \inst5|CLK_OUT~I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_16
cyclone_io \20mclk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\20mclk~combout ),
	.regout(),
	.padio(\20mclk ));
// synopsys translate_off
defparam \20mclk~I .input_async_reset = "none";
defparam \20mclk~I .input_power_up = "low";
defparam \20mclk~I .input_register_mode = "none";
defparam \20mclk~I .input_sync_reset = "none";
defparam \20mclk~I .oe_async_reset = "none";
defparam \20mclk~I .oe_power_up = "low";
defparam \20mclk~I .oe_register_mode = "none";
defparam \20mclk~I .oe_sync_reset = "none";
defparam \20mclk~I .operation_mode = "input";
defparam \20mclk~I .output_async_reset = "none";
defparam \20mclk~I .output_power_up = "low";
defparam \20mclk~I .output_register_mode = "none";
defparam \20mclk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X26_Y6_N4
cyclone_lcell \inst2|Selector11~81_I (
// Equation(s):
// \inst2|Selector11~81  = \inst10|CLKN  & (\inst2|STATE.p10ms  # \inst2|STATE.p1ms )

	.clk(gnd),
	.dataa(vcc),
	.datab(\inst2|STATE.p10ms ),
	.datac(\inst10|CLKN ),
	.datad(\inst2|STATE.p1ms ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|Selector11~81 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|Selector11~81_I .lut_mask = "F0C0";
defparam \inst2|Selector11~81_I .operation_mode = "normal";
defparam \inst2|Selector11~81_I .output_mode = "comb_only";
defparam \inst2|Selector11~81_I .register_cascade_mode = "off";
defparam \inst2|Selector11~81_I .sum_lutc_input = "datac";
defparam \inst2|Selector11~81_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X24_Y6_N0
cyclone_lcell \inst2|Selector11~82_I (
// Equation(s):
// \inst2|Selector11~82  = \inst2|Selector11~81  # \inst5|CLK_OUT  & (\inst2|STATE.p10s  # \inst2|STATE.overflowl )

	.clk(gnd),
	.dataa(\inst2|STATE.p10s ),
	.datab(\inst2|STATE.overflowl ),
	.datac(\inst2|Selector11~81 ),
	.datad(\inst5|CLK_OUT ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|Selector11~82 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|Selector11~82_I .lut_mask = "FEF0";
defparam \inst2|Selector11~82_I .operation_mode = "normal";
defparam \inst2|Selector11~82_I .output_mode = "comb_only";
defparam \inst2|Selector11~82_I .register_cascade_mode = "off";
defparam \inst2|Selector11~82_I .sum_lutc_input = "datac";
defparam \inst2|Selector11~82_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X26_Y5_N4
cyclone_lcell \inst4|CLK_OUT~I (
// Equation(s):
// \inst4|CLK_OUT  = DFFEAS(\inst4|COUNT [2] & (\inst4|CLK_OUT  # !\inst4|CLK_OUT~95  & \inst4|COUNT [0]) # !\inst4|COUNT [2] & \inst4|CLK_OUT  & (\inst4|CLK_OUT~95  # \inst4|COUNT [0]), GLOBAL(\inst11|CLK_OUT ), VCC, , , , , , )

	.clk(\inst11|CLK_OUT ),
	.dataa(\inst4|COUNT [2]),
	.datab(\inst4|CLK_OUT~95 ),
	.datac(\inst4|CLK_OUT ),
	.datad(\inst4|COUNT [0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst4|CLK_OUT ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst4|CLK_OUT~I .lut_mask = "F2E0";
defparam \inst4|CLK_OUT~I .operation_mode = "normal";
defparam \inst4|CLK_OUT~I .output_mode = "reg_only";
defparam \inst4|CLK_OUT~I .register_cascade_mode = "off";
defparam \inst4|CLK_OUT~I .sum_lutc_input = "datac";
defparam \inst4|CLK_OUT~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X26_Y6_N5
cyclone_lcell \inst2|Selector11~83_I (
// Equation(s):
// \inst2|Selector11~83  = \inst2|STATE.p100ms  & (\inst11|CLK_OUT  # \inst4|CLK_OUT  & \inst2|STATE.p1s ) # !\inst2|STATE.p100ms  & \inst4|CLK_OUT  & (\inst2|STATE.p1s )

	.clk(gnd),
	.dataa(\inst2|STATE.p100ms ),
	.datab(\inst4|CLK_OUT ),
	.datac(\inst11|CLK_OUT ),
	.datad(\inst2|STATE.p1s ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|Selector11~83 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|Selector11~83_I .lut_mask = "ECA0";