📄 ifx_nand.h
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/*
* NAND Flash hardware definition for INCA-IP development board.
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* ########################################################################
*
* ifx_nand.h
*
* Description:
* device driver of NAND controller of INCA-IP chip
* Author:
* Winder Sung
* Created:
* 20 NOV 2005
* History & Modification Tag:
* ___________________________________________________________________________
* | Tag | Comments | Modifier & Time |
* |--------+---------------------------------------------+------------------|
* | 0.0 | First version of this driver and the tag is | Winder Sung |
* | | implied. | 20 NOV 2005 |
* ---------------------------------------------------------------------------
*
*/
/*
* Common Head File
*/
#include <asm/inca-ip.h>
#include <asm/addrspace.h>
#ifdef NAND_DEBUG
#define NANDPRINT printf
#else
#define NANDPRINT(fmt,args...)
#endif
/*
* Chip Specific Head File
*/
#define CLE_ADDR_BIT 0x01
#define ALE_ADDR_BIT 0x02
/*
* ####################################
* Parameters to Configure NAND
* ####################################
*/
/*
* ####################################
* Definition
* ####################################
*/
/*
* NAND Flash Device RD/BY State Register
*/
#define NAND_WAIT_RD ((*INCA_IP_Ports_P1_IN & (1 << 17)) == (1 << 17) ? 1 : 0)
/*
* ####################################
* Declaration
* ####################################
*/
// select chip
#define NAND_ENABLE_CE(nand) do{*INCA_IP_Ports_P1_OUT &= ~(1 << 16);}while(0)
// de-select chip
#define NAND_DISABLE_CE(nand) do{*INCA_IP_Ports_P1_OUT |= (1 << 16);}while(0)
// Assert the CLE (Command Latch Enable) line to the flash chip
#define NAND_CTL_SETCLE(nandptr) do{(unsigned long) nandptr |= CLE_ADDR_BIT;}while(0)
// Lower the CLE line
#define NAND_CTL_CLRCLE(nandptr) do{(unsigned long) nandptr &= ~CLE_ADDR_BIT;}while(0)
// Assert the ALE (Adress Latch Enable) line to the flash chip
#define NAND_CTL_SETALE(nandptr) do{(unsigned long) nandptr |= ALE_ADDR_BIT;}while(0)
// Lower the ALE line
#define NAND_CTL_CLRALE(nandptr) do{(unsigned long) nandptr &= ~ALE_ADDR_BIT;}while(0)
// Write Command
#define WRITE_NAND_COMMAND(d, adr) do{*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d);NANDPRINT("CMD:%x\n", d);} while(0)
// Write Address
#define WRITE_NAND_ADDRESS(d, adr) do{*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d);NANDPRINT("ADDR:%x\n", d);} while(0)
//Write Data
#define WRITE_NAND(d, adr) do{*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d);NANDPRINT("%x", d);} while(0)
// Read Date
#define READ_NAND(adr) ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
// Wait device ready, write complete
#define NAND_WAIT_READY_CMD(nand) do{NANDPRINT("Wait for write complete!!\n");}while(0)
#define NAND_WAIT_READY(nand) do{/*NANDPRINT("%x", NAND_WAIT_RD);*/udelay(12);while(!NAND_WAIT_RD){udelay(1);}}while(0)
#define NAND_WAIT_READY_RESET(nand) do{/*NANDPRINT("%x\n", NAND_WAIT_RD);*/udelay(12);while(!NAND_WAIT_RD){udleay(1);}}while(0)
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