ssc.c

基于mips CPU

#include <common.h>
#include <asm/inca-ip.h>

#if defined(CONFIG_SERIAL_FLASH) || defined(CONFIG_DISPLAY)

extern uint incaip_get_fpiclk (void);

int ssc_init(void)
{	
	/* enable SSC1 */
	*INCA_IP_PMU_PM_GEN |= INCA_IP_PMU_PM_GEN_EN11;
	
	/* SSC1 Ports */
	/* set pin 6-8 to default function: P2_ALTSEL */
	*INCA_IP_Ports_P2_ALTSEL &= ~0x1c0;	/* P2.6, P2.7 and P2.8 set to default */	
	*INCA_IP_Ports_P2_DIR &= ~(0x0080);	/* P2.7 direction input */
	*INCA_IP_Ports_P2_DIR |= (0x0140);	/* P2.6 and P2.8 direction out */
	
	/* clear all interrupts */
	*INCA_IP_ICU_IM2_ISR = 0x380;
	/* enable all interrupts */
	*INCA_IP_ICU_IM2_IER |= 0x380;
	/* *INCA_IP_ICU_IM2_IER &= 0x100; */
	
	
	/* Clock Control Register */
	/* DISS OFF and RMC = 1 */
	*INCA_IP_SSC1_SSC_CLC &= ~INCA_IP_SSC1_SSC_CLC_DISS;
	*INCA_IP_SSC1_SSC_CLC |= INCA_IP_SSC1_SSC_CLC_RMC(1);	/* fssc = ffpi */
	
	/* Control Register */
	
	/* Disable SSC to get access to the control bits */
	*INCA_IP_SSC1_SCC_CON_PRG &= ~INCA_IP_SSC1_SCC_CON_PRG_EN;
	
	*INCA_IP_SSC1_SCC_CON_PRG |= INCA_IP_SSC1_SCC_CON_PRG_MS;
	
	*INCA_IP_SSC1_SSC_WHBCON |= INCA_IP_SSC1_SSC_WHBCON_CLRBE;	/* Baud errors ignored */
	*INCA_IP_SSC1_SSC_WHBCON |= INCA_IP_SSC1_SSC_WHBCON_CLRPE;	/* Phase errors ignored */
	*INCA_IP_SSC1_SSC_WHBCON |= INCA_IP_SSC1_SSC_WHBCON_CLRRE;	/* Receive errors ignored */
	*INCA_IP_SSC1_SSC_WHBCON |= INCA_IP_SSC1_SSC_WHBCON_CLRTE;	/* Transmit errors ignored */
	
	*INCA_IP_SSC1_SCC_CON_PRG &= ~INCA_IP_SSC1_SCC_CON_PRG_LB;	/* Loopback off */
	*INCA_IP_SSC1_SCC_CON_PRG |= INCA_IP_SSC1_SCC_CON_PRG_PO;	/* Idle clock high */
	*INCA_IP_SSC1_SCC_CON_PRG &= ~INCA_IP_SSC1_SCC_CON_PRG_PH;	/* Transmit on leading edge */
	*INCA_IP_SSC1_SCC_CON_PRG &= ~INCA_IP_SSC1_SCC_CON_PRG_HB;	/* LSB First */
	
	*INCA_IP_SSC1_SCC_CON_PRG |= INCA_IP_SSC1_SCC_CON_PRG_BM(DATA_WIDTH-1);
	
	/* Set the Baudrate */
	/*
	 * BR = (FPI clk / (2 * Baudrate)) - 1
	 * Note: Must be set while SSC is disabled!
	 */
	*INCA_IP_SSC1_SSC_BR |= INCA_IP_SSC1_SSC_BR_BR_VALUE((incaip_get_fpiclk()>>1)/BAUD_RATE-1);

	/* Enable SSC */
	*INCA_IP_SSC1_SCC_CON_OPR |= INCA_IP_SSC1_SCC_CON_OPR_EN;
	
	*INCA_IP_SSC1_SSC_RB = 0xFFFF;
	
	return 0;
}

int ssc_close(void)
{
	*INCA_IP_SSC1_SSC_CLC = 0x00000002;

	*INCA_IP_Ports_P2_ALTSEL &= ~(1 << 15);
	
	/* disable SSC1 */
	*INCA_IP_PMU_PM_GEN &= ~INCA_IP_PMU_PM_GEN_EN11;
	
	return 0;	
}

int ssc_read(unsigned char *uc_value)
{
	*uc_value = ((*INCA_IP_SSC1_SSC_RB) & 0xFFFF);
	while(((*INCA_IP_SSC1_SCC_CON_OPR) & INCA_IP_SSC1_SCC_CON_OPR_BSY) == INCA_IP_SSC1_SCC_CON_OPR_BSY);
	/* Clear all interrupts */
	*INCA_IP_ICU_IM2_ISR = 0x380;
	return 0;
}


int ssc_write(unsigned char uc_value)
{
	*INCA_IP_SSC1_SSC_TB = uc_value;
	while(((*INCA_IP_SSC1_SCC_CON_OPR) & INCA_IP_SSC1_SCC_CON_OPR_BSY) == INCA_IP_SSC1_SCC_CON_OPR_BSY);
	/* Clear all interrupts */
	*INCA_IP_ICU_IM2_ISR = 0x380;
	return 0;
}

int ssc_clear_interrupts(void)
{
	*INCA_IP_ICU_IM2_ISR = 0x380;
	return 0;
}
 
#endif /* CONFIG_SERIAL_FLASH or CONFIG_DISPLAY */