incaip_nand.c

基于mips CPU

#include <common.h>

#ifdef NEW_VERSION_NAND_SUPPORT

#include <asm/inca-ip.h>

#if (CONFIG_COMMANDS && CFG_CMD_NAND)

#include <linux/mtd/nand.h>


/* Hardware control function */
static void incaip_hwcontrol (struct mtd_info *mtd, int cmd)
{
	struct nand_chip *this = (struct nand_chip *) mtd->priv;

	switch (cmd) {
		case NAND_CTL_SETCLE:
			(unsigned long) this->IO_ADDR_W |= CLE_ADDR_BIT;
			break;
		case NAND_CTL_CLRCLE:
			(unsigned long) this->IO_ADDR_W &= ~CLE_ADDR_BIT;
			break;
		case NAND_CTL_SETALE:
			(unsigned long) this->IO_ADDR_W |= ALE_ADDR_BIT;
			break;
		case NAND_CTL_CLRALE:
			(unsigned long) this->IO_ADDR_W &= ~ALE_ADDR_BIT;
			break;
		case NAND_CTL_SETNCE:
			*INCA_IP_Ports_P1_OUT &= ~(1 << 16);
			break;
		case NAND_CTL_CLRNCE:
			*INCA_IP_Ports_P1_OUT |= (1 << 16);
			break;
	}
}

/* Device ready function */
int incaip_dev_ready (struct mtd_info *mtd)
{
	return ((*INCA_IP_Ports_P1_IN & (1 << 17)) == (1 << 17) ? 1 : 0);
}


/* Initialize hardware to support NAND device */
void incaip_hwinit (void) 
{
	/* Initialize port 1.16 for the NAND enable */
	*INCA_IP_Ports_P1_ALTSEL |= (1 << 16);	/* P1.16 set to GPIO */
	*INCA_IP_Ports_P1_DIR    |= (1 << 16);	/* P1.16 direction output */
	*INCA_IP_Ports_P1_OUT    |= (1 << 16);	/* Chipselect is at high */

	/* Initialize port 1.17 for Ready/Busy pin */
	*INCA_IP_Ports_P1_ALTSEL |= (1 << 17);	/* P1.17 set to GPIO */
	*INCA_IP_Ports_P1_DIR    &= ~(1 << 17);	/* P1.17 direction input*/
	
	/* Initialize register EBU_ADDSEL1 for CS0 */
	*INCA_IP_EBU_EBU_ADDSEL1 &= 0xBE0000F1;

	/* EBU_BUSCON1 */
	*INCA_IP_EBU_EBU_BUSCON1 = 0x4000D7FF;
}

/* Board initialization function */
void board_nand_init (struct nand_chip *nand) 
{
	
	/* Set hardware control function */
	nand->hwcontrol = incaip_hwcontrol;

	/* Assign the device ready function */
	nand->dev_ready = incaip_dev_ready;

	nand->eccmode = NAND_ECC_SOFT;

	/* Initialize relevant ports and the EBU register */
	incaip_hwinit();

	/* Buffers are allocated in the nand_scan function */
	return;
}

#endif /* CFG_CMD_NAND */

#endif // NEW_VERSION_NAND_SUPPORT