ps2_wb_if.v

ps2接口源程序。标准的键盘和鼠标接口

                  current_command_output_valid  = 1'b1 ;
              end
        8'hA5:begin
                  current_command_gets_null_terminated_string = 1'b1 ;
              end
        8'hA6:begin
              end
        8'hA7:begin
              end
        8'hA8:begin
              end
        8'hA9:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output_valid  = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_output        = 8'h00 ;  // interface OK
                  `else
                  current_command_output        = 8'h02 ; // clock line stuck high
                  `endif
              end
        8'hAA:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h55 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAB:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAD:begin
              end
        8'hAE:begin
              end
        8'hAF:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC1:begin
              end
        8'hC2:begin
              end
        8'hD0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h01 ; // only system reset bit is 1
                  current_command_output_valid  = 1'b1 ;
              end
        8'hD1:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hD2:begin
                  current_command_returns_value   = 1'b1 ;
                  current_command_gets_parameter  = 1'b1 ;
                  current_command_output          = output_buffer ;
                  current_command_output_valid    = write_output_buffer_reg_previous ;
              end
        8'hD3:begin
                  current_command_gets_parameter = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_returns_value  = 1'b1 ;
                  current_command_output         = output_buffer ;
                  current_command_output_valid   = write_output_buffer_reg_previous ;
                  `endif
              end
        8'hD4:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hE0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
    endcase
end

reg cyc_i_previous ;
reg stb_i_previous ;

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else if ( wb_ack_o )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else
    begin
        cyc_i_previous <= #1 wb_cyc_i ;
        stb_i_previous <= #1 wb_stb_i ;
    end

end

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_ack_o <= #1 1'b0 ;
    else if ( wb_ack_o )
        wb_ack_o <= #1 1'b0 ;
    else
        wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;
end

reg [31:0] wb_dat_o ;
wire wb_read = read_input_buffer_reg || read_status_register_reg || read_devide ;

wire [15:0] output_data = read_status_register_reg ? {2{status_byte}} : read_devide ? devide_reg : {2{input_buffer}} ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_dat_o <= #1 32'h0 ;
    else if ( wb_read )
        wb_dat_o <= #1 {2{output_data}} ;
end

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer_full <= #1 1'b0 ;
    else if ( output_buffer_full && tx_kbd_write_ack_i || enable1)
        output_buffer_full <= #1 1'b0 ;
    else
        output_buffer_full <= #1 write_output_buffer_reg && (!current_command_valid || (!current_command_gets_parameter && !current_command_gets_null_terminated_string)) ;
end

`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_output_buffer_full <= #1 1'b0 ;
    else if ( aux_output_buffer_full && tx_aux_write_ack_i || enable2)
        aux_output_buffer_full <= #1 1'b0 ;
    else
        aux_output_buffer_full <= #1 write_output_buffer_reg && current_command_valid && (current_command == 8'hD4) ;
end
`endif

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer <= #1 8'h00 ;
    else if ( write_output_buffer_reg )
        output_buffer <= #1 wb_dat_i_sampled[15:8];
end

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        devide_reg <= #1 8'h00 ;
    else 
      begin
      if ( write_devide_reg0 )
        devide_reg[7:0] <= #1 wb_dat_i_sampled[7:0] ;
      if ( write_devide_reg1 )
        devide_reg[15:8] <= #1 wb_dat_i_sampled[15:8] ;
      end
end

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        translate_o <= #1 1'b0 ;
        system      <= #1 1'b0 ;
        interrupt1  <= #1 1'b0 ;
        `ifdef PS2_AUX
        interrupt2  <= #1 1'b0 ;
        `endif
    end
    else if ( write_command_byte )
    begin
        translate_o <= #1 output_buffer[6] ;
        system      <= #1 output_buffer[2] ;
        interrupt1  <= #1 output_buffer[0] ;
        `ifdef PS2_AUX
        interrupt2  <= #1 output_buffer[1] ;
        `endif
    end
end

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable1 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hAE) )
        enable1 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hAD) )
        enable1 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable1 <= #1 output_buffer[4] ;

end

`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable2 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hA8) )
        enable2 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hA7) )
        enable2 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable2 <= #1 output_buffer[5] ;

end
`endif

wire write_input_buffer_from_command = current_command_valid && current_command_returns_value && current_command_output_valid ;
wire write_input_buffer_from_kbd     = !input_buffer_full && rx_kbd_data_ready_i && !enable1 && !current_command_valid ;

`ifdef PS2_AUX
wire write_input_buffer_from_aux     = !input_buffer_full && rx_aux_data_ready_i && !enable2 && !current_command_valid && !write_input_buffer_from_kbd ;
`endif

wire load_input_buffer_value =
    write_input_buffer_from_command
    ||
    write_input_buffer_from_kbd
    `ifdef PS2_AUX
    ||
    write_input_buffer_from_aux
    `endif
    ;

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_full <= #1 1'b0 ;
    else if ( load_input_buffer_value )
        input_buffer_full <= #1 1'b1 ;
end

`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( write_input_buffer_from_aux || (write_input_buffer_from_command && (current_command == 8'hD3)) )
        aux_input_buffer_full <= #1 1'b1 ;
end
`endif

reg input_buffer_filled_from_command ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( write_input_buffer_from_command )
        input_buffer_filled_from_command <= #1 1'b1 ;
end

`ifdef PS2_AUX
reg [7:0] value_to_load_in_input_buffer ;
always@
(
    write_input_buffer_from_command
    or
    current_command_output
    or
    rx_scancode_i
    or
    write_input_buffer_from_kbd
    or
    rx_aux_data_i
)
begin
    case ({write_input_buffer_from_command, write_input_buffer_from_kbd})
        2'b10,
        2'b11   :   value_to_load_in_input_buffer = current_command_output ;
        2'b01   :   value_to_load_in_input_buffer = rx_scancode_i ;
        2'b00   :   value_to_load_in_input_buffer = rx_aux_data_i ;
    endcase
end

`else
wire [7:0] value_to_load_in_input_buffer = write_input_buffer_from_command ? current_command_output : rx_scancode_i ;
`endif

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer <= #1 8'h00 ;
    else if ( load_input_buffer_value )
        input_buffer <= #1 value_to_load_in_input_buffer ;
end

assign rx_kbd_read_o = rx_kbd_data_ready_i &&
                       ( enable1
                         ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                           `ifdef PS2_AUX
                           &&
                           !aux_input_buffer_full
                           `endif
                          )
                        );

`ifdef PS2_AUX
assign rx_aux_read_o = rx_aux_data_ready_i &&
                       ( enable2 ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           aux_input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                          )
                        );
`endif

always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_int_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable1 || !interrupt1)
        wb_int_o <= #1 1'b0 ;
    else
        wb_int_o <= #1 input_buffer_full
                       `ifdef PS2_AUX
                       &&
                       !aux_input_buffer_full
                       `endif
                       ;
end

`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_intb_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable2 || !interrupt2)
        wb_intb_o <= #1 1'b0 ;
    else
        wb_intb_o <= #1 input_buffer_full
                       &&
                       aux_input_buffer_full
                       ;
end
`endif

endmodule // ps2_wb_if