scan_divf_sinx2.vhd

正弦信号发生器（可扫频）通过验证 正弦信号发生器

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY scan_divf_sinx2 IS
    PORT(  clock,enable: IN  STD_LOGIC;         
           fin:out std_logic;
           da_data: out integer range 255 downto 0
        );
END;

ARCHITECTURE behav OF scan_divf_sinx2 IS

component SCANCNT4B
    port(  CLK: IN  STD_LOGIC;
           EN: IN STD_LOGIC;
           FOUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
         );
end component;
component divf
    port(  CLK: IN  STD_LOGIC;
           DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           FOUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           COUT: OUT STD_LOGIC
         );
end component;
component singt4
    port( clk:in std_logic;
          cout:out std_logic;
          dout: out integer range 255 downto 0
         );
end component; 
signal f:std_logic;
signal d:std_logic_vector(3 downto 0);
--signal c:std_logic;  
  begin
u1: SCANCNT4B port map( en=>enable,clk=>clock,fout=>d );
u2: divf port map( CLK=>clock,DATA=>d,COUT=>f );
u3: singt4 port map( clk=>f,dout=>da_data,cout=>fin );  
end;