scan_divf_sinx2.tan.rpt

正弦信号发生器（可扫频）通过验证 正弦信号发生器

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 14 22:18:08 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off scan_divf_sinx2 -c scan_divf_sinx2
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "divf:u2|COUT" as buffer
Info: Clock "clock" has Internal fmax of 79.37 MHz between source register "singt4:u3|q[2]" and destination register "singt4:u3|q[6]" (period= 12.6 ns)
    Info: + Longest register to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C13; Fanout = 49; REG Node = 'singt4:u3|q[2]'
        Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC3_C14; Fanout = 2; COMB Node = 'singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.700 ns; Loc. = LC4_C14; Fanout = 2; COMB Node = 'singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC5_C14; Fanout = 2; COMB Node = 'singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC6_C14; Fanout = 1; COMB Node = 'singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 6: + IC(0.000 ns) + CELL(1.300 ns) = 5.600 ns; Loc. = LC7_C14; Fanout = 1; COMB Node = 'singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[6]'
        Info: 7: + IC(2.200 ns) + CELL(1.200 ns) = 9.000 ns; Loc. = LC8_C13; Fanout = 10; REG Node = 'singt4:u3|q[6]'
        Info: Total cell delay = 4.600 ns ( 51.11 % )
        Info: Total interconnect delay = 4.400 ns ( 48.89 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 10.900 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 8; REG Node = 'divf:u2|COUT'
            Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC8_C13; Fanout = 10; REG Node = 'singt4:u3|q[6]'
            Info: Total cell delay = 3.900 ns ( 35.78 % )
            Info: Total interconnect delay = 7.000 ns ( 64.22 % )
        Info: - Longest clock path from clock "clock" to source register is 10.900 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 8; REG Node = 'divf:u2|COUT'
            Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC2_C13; Fanout = 49; REG Node = 'singt4:u3|q[2]'
            Info: Total cell delay = 3.900 ns ( 35.78 % )
            Info: Total interconnect delay = 7.000 ns ( 64.22 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "enable", clock pin = "clock") is 3.300 ns
    Info: + Longest pin to register delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 14; PIN Node = 'enable'
        Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 4.500 ns ( 73.77 % )
        Info: Total interconnect delay = 1.600 ns ( 26.23 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "clock" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "clock" to destination pin "da_data[0]" through register "singt4:u3|q[1]" is 38.000 ns
    Info: + Longest clock path from clock "clock" to source register is 10.900 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'
        Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 8; REG Node = 'divf:u2|COUT'
        Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC8_C14; Fanout = 46; REG Node = 'singt4:u3|q[1]'
        Info: Total cell delay = 3.900 ns ( 35.78 % )
        Info: Total interconnect delay = 7.000 ns ( 64.22 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 26.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_C14; Fanout = 46; REG Node = 'singt4:u3|q[1]'
        Info: 2: + IC(4.600 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC4_A9; Fanout = 1; COMB Node = 'singt4:u3|dout[0]~652'
        Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC2_A9; Fanout = 1; COMB Node = 'singt4:u3|dout[0]~653'
        Info: 4: + IC(2.700 ns) + CELL(2.300 ns) = 14.800 ns; Loc. = LC5_A17; Fanout = 1; COMB Node = 'singt4:u3|dout[0]~655'
        Info: 5: + IC(2.200 ns) + CELL(2.300 ns) = 19.300 ns; Loc. = LC5_A21; Fanout = 1; COMB Node = 'singt4:u3|dout[0]~656'
        Info: 6: + IC(1.600 ns) + CELL(5.100 ns) = 26.000 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'da_data[0]'
        Info: Total cell delay = 14.300 ns ( 55.00 % )
        Info: Total interconnect delay = 11.700 ns ( 45.00 % )
Info: th for register "SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "enable", clock pin = "clock") is 1.300 ns
    Info: + Longest clock path from clock "clock" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 14; PIN Node = 'enable'
        Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 4.000 ns ( 71.43 % )
        Info: Total interconnect delay = 1.600 ns ( 28.57 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Apr 14 22:18:10 2006
    Info: Elapsed time: 00:00:03