mif1.tan.qmsg

存储示波器

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 26 " "Warning: Circuit may not operate. Detected 26 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] CLK 700 ps " "Info: Found hold time violation between source  pin or register \"CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination pin or register \"CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" for clock \"CLK\" (Hold time is 700 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.900 ns + Largest " "Info: + Largest clock skew is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 7; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 16 -200 -32 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ADCINT:inst\|current_state.st4 2 REG LC3_F9 11 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC3_F9; Fanout = 11; REG Node = 'ADCINT:inst\|current_state.st4'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK ADCINT:inst|current_state.st4 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "C:/cunchuqi/ADCINT.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 4.600 ns CNT10B:inst1\|CLKOUT~3 3 COMB LC1_F9 177 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 4.600 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 7.400 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 4 REG LC5_D16 19 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 52.70 % ) " "Info: Total cell delay = 3.900 ns ( 52.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 47.30 % ) " "Info: Total interconnect delay = 3.500 ns ( 47.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.800ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 7; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 16 -200 -32 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.600 ns) 3.700 ns CNT10B:inst1\|CLKOUT~3 2 COMB LC1_F9 177 " "Info: 2: + IC(0.100 ns) + CELL(1.600 ns) = 3.700 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { CLK CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 6.500 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 3 REG LC5_D16 19 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 6.500 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 55.38 % ) " "Info: Total cell delay = 3.600 ns ( 55.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 44.62 % ) " "Info: Total interconnect delay = 2.900 ns ( 44.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { CLK CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.100ns 2.800ns } { 0.000ns 2.000ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.800ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { CLK CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.100ns 2.800ns } { 0.000ns 2.000ns 1.600ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns - " "Info: - Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.000 ns - Shortest register register " "Info: - Shortest register to register delay is 1.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC5_D16 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC5_D16 19 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 100.00 % ) " "Info: Total cell delay = 1.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.000 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns } { 0.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.800ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { CLK CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.100ns 2.800ns } { 0.000ns 2.000ns 1.600ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.000 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns } { 0.000ns 1.000ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "ADCINT:inst\|current_state.st3 EOC CLK 8.100 ns register " "Info: tsu for register \"ADCINT:inst\|current_state.st3\" (data pin = \"EOC\", clock pin = \"CLK\") is 8.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.900 ns + Longest pin register " "Info: + Longest pin to register delay is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns EOC 1 PIN PIN_20 2 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_20; Fanout = 2; PIN Node = 'EOC'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { EOC } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 48 -240 -72 64 "EOC" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(1.000 ns) 9.900 ns ADCINT:inst\|current_state.st3 2 REG LC2_F9 2 " "Info: 2: + IC(4.000 ns) + CELL(1.000 ns) = 9.900 ns; Loc. = LC2_F9; Fanout = 2; REG Node = 'ADCINT:inst\|current_state.st3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { EOC ADCINT:inst|current_state.st3 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "C:/cunchuqi/ADCINT.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.900 ns ( 59.60 % ) " "Info: Total cell delay = 5.900 ns ( 59.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 40.40 % ) " "Info: Total interconnect delay = 4.000 ns ( 40.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.900 ns" { EOC ADCINT:inst|current_state.st3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.900 ns" { EOC EOC~out ADCINT:inst|current_state.st3 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 4.900ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "ADCINT.vhd" "" { Text "C:/cunchuqi/ADCINT.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 7; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 16 -200 -32 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ADCINT:inst\|current_state.st3 2 REG LC2_F9 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_F9; Fanout = 2; REG Node = 'ADCINT:inst\|current_state.st3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK ADCINT:inst|current_state.st3 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "C:/cunchuqi/ADCINT.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK ADCINT:inst|current_state.st3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out ADCINT:inst|current_state.st3 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.900 ns" { EOC ADCINT:inst|current_state.st3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.900 ns" { EOC EOC~out ADCINT:inst|current_state.st3 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 4.900ns 1.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK ADCINT:inst|current_state.st3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out ADCINT:inst|current_state.st3 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}