prev_cmp_mif1.tan.qmsg

存储示波器

{ "Info" "ITDB_FULL_TCO_RESULT" "WREN Q\[7\] ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_ra0 30.100 ns memory " "Info: tco from clock \"WREN\" to destination pin \"Q\[7\]\" through memory \"ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_ra0\" is 30.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WREN source 13.600 ns + Longest memory " "Info: + Longest clock path from clock \"WREN\" to source memory is 13.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns WREN 1 CLK PIN_8 9 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 9; CLK Node = 'WREN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WREN } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 168 -264 -96 184 "WREN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.600 ns) 10.800 ns CNT10B:inst1\|CLKOUT~3 2 COMB LC1_F9 177 " "Info: 2: + IC(4.300 ns) + CELL(1.600 ns) = 10.800 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { WREN CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 13.600 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_ra0 3 MEM EC4_D 1 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 13.600 ns; Loc. = EC4_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_ra0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.500 ns ( 47.79 % ) " "Info: Total cell delay = 6.500 ns ( 47.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 52.21 % ) " "Info: Total interconnect delay = 7.100 ns ( 52.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.100 ns + Longest memory pin " "Info: + Longest memory to pin delay is 16.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_ra0 1 MEM EC4_D 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC4_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_ra0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 4.400 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~mem_cell_ra0 2 MEM EC4_D 1 " "Info: 2: + IC(0.000 ns) + CELL(4.400 ns) = 4.400 ns; Loc. = EC4_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~mem_cell_ra0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~mem_cell_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 5.800 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\] 3 MEM EC4_D 1 " "Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 5.800 ns; Loc. = EC4_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~mem_cell_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 9.000 ns Q\[7\]~0 4 COMB LC1_D31 1 " "Info: 4: + IC(1.800 ns) + CELL(1.400 ns) = 9.000 ns; Loc. = LC1_D31; Fanout = 1; COMB Node = 'Q\[7\]~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] Q[7]~0 } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 176 528 704 192 "Q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(6.300 ns) 16.100 ns Q\[7\] 5 PIN PIN_41 0 " "Info: 5: + IC(0.800 ns) + CELL(6.300 ns) = 16.100 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'Q\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { Q[7]~0 Q[7] } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 176 528 704 192 "Q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.500 ns ( 83.85 % ) " "Info: Total cell delay = 13.500 ns ( 83.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 16.15 % ) " "Info: Total interconnect delay = 2.600 ns ( 16.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~mem_cell_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] Q[7]~0 Q[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~mem_cell_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] Q[7]~0 Q[7] } { 0.000ns 0.000ns 0.000ns 1.800ns 0.800ns } { 0.000ns 4.400ns 1.400ns 1.400ns 6.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~mem_cell_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] Q[7]~0 Q[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~mem_cell_ra0 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] Q[7]~0 Q[7] } { 0.000ns 0.000ns 0.000ns 1.800ns 0.800ns } { 0.000ns 4.400ns 1.400ns 1.400ns 6.300ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_we0 WREN WREN 4.600 ns memory " "Info: th for memory \"ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_we0\" (data pin = \"WREN\", clock pin = \"WREN\") is 4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WREN destination 13.600 ns + Longest memory " "Info: + Longest clock path from clock \"WREN\" to destination memory is 13.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns WREN 1 CLK PIN_8 9 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 9; CLK Node = 'WREN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WREN } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 168 -264 -96 184 "WREN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.600 ns) 10.800 ns CNT10B:inst1\|CLKOUT~3 2 COMB LC1_F9 177 " "Info: 2: + IC(4.300 ns) + CELL(1.600 ns) = 10.800 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { WREN CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 13.600 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_we0 3 MEM EC4_D 1 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 13.600 ns; Loc. = EC4_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~reg_we0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_we0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.500 ns ( 47.79 % ) " "Info: Total cell delay = 6.500 ns ( 47.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 52.21 % ) " "Info: Total interconnect delay = 7.100 ns ( 52.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_we0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7]~reg_we0 } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.500 ns + " "Info: + Micro hold delay of destination is